FN6660 Rev 8.00 Page 1 of 16
September 2, 2016
FN6660
Rev 8.00
September 2, 2016
ISL80102, ISL80103
High Performance 2A and 3A Linear Regulators
DATASHEET
The ISL80102 and ISL80103 are low voltage, high-current,
single output LDOs specified for 2A and 3A output current,
respectively. These LDOs operate from the input voltages of
2.2V to 6V and are capable of providing the output voltages of
0.8V to 5.5V on the adjustable V
OUT
versions. Other custom
voltage options available upon request.
For applications that demand inrush current less than the
current limit, an external capacitor on the soft-start pin
provides adjustment. The ENABLE feature allows the part to be
placed into a low quiescent current shutdown mode. A
submicron BiCMOS process is utilized for this product family to
deliver the best-in-class analog performance and overall value.
These CMOS (LDOs) will consume significantly lower quiescent
current as a function of load over bipolar LDOs, which
translates into higher efficiency and the ability to consider
packages with smaller footprints. The quiescent current has
been modestly compromised to enable a leading class fast
load transient response, and hence a lower total AC regulation
band for an LDO in this category.
Features
• Stable with ceramic capacitors (Note 11)
• 2A and 3A output current ratings
• 2.2V to 6V input voltage range
•±1.8% V
OUT
accuracy guaranteed over line, load and
T
J
= -40°C to +125°C
• Very low 120mV dropout voltage at 3A (ISL80103)
• Very fast transient response
• Excellent 62dB PSRR
• 49µV
RMS
output noise
• Power-good output
• Adjustable inrush current limiting
• Short-circuit and over-temperature protection
• Available in a 10 Ld DFN
Applications
•Servers
• Telecommunications and networking
• Medical equipment
• Instrumentation systems
•Routers and switchers
FIGURE 1. TYPICAL APPLICATION FOR FIXED OUTPUT VOLTAGE VERSION
ISL80102, ISL80103
V
IN
9
V
IN
10
ENABLE
7
SS
6
GND
2.5V ±10%
C
IN
10µF
V
IN
OFF
ON
*C
SS
5
PG
4
V
OUT
1
V
OUT
2
V
OUT
1.8V ±1.8%
C
OUT
10µF
R
PG
100kΩ
SENSE
3
PGOOD
*CSS is optional, (see Note 12 on page 5).
ISL80102, ISL80103
FN6660 Rev 8.00 Page 2 of 16
September 2, 2016
Pin Configuration
ISL80102, ISL80103
(10 LD 3x3 DFN)
TOP VIEW
FIGURE 2. TYPICAL APPLICATION DIAGRAM FOR ADJUSTABLE OUTPUT VOLTAGE VERSION
ISL80102, ISL80103
V
IN
9
V
IN
10
ENABLE
7
SS
6
GND
2.5V ±10%
C
IN
10µF
V
IN
*C
SS
5
PG
4
V
OUT
1
V
OUT
2
V
OUT
1.8V
C
OUT
10µF
R
PG
100kΩ
ADJ
3
PGOOD
R
1
10kΩ
R
4
1.0kΩ
**C
PB
47pF
EN
OPEN DRAIN COMPATIBLE
*CSS is optional, (see Note 12 on page 5).
**C
PB
is optional. See “Functional Description” on page 12 for more information.
R
3
2.61kΩ
TABLE 1. COMPONENTS VALUE SELECTION
V
OUT
(V)
R
TOP
(kΩ)
R
BOTTOM
(Ω)
C
PB
(pF)
C
OUT
(µF)
5.0 2.61 287 47 10
3.3 2.61 464 47 10
2.5 2.61 649 47 10
1.8
(Note 1) 2.61 1.0k 47 10
1.8
(Note 1) 2.61 1.0k 82 22
1.5 2.61 1.3k 82 22
1.2 2.61 1.87k 150 47
1.0 2.61 2.61k 150 47
0.8 2.61 4.32k 150 47
NOTE:
1. Either option could be used depending on cost/performance
requirements
2
3
4
1
5
9
8
7
10
6
V
OUT
V
OUT
SENSE/ADJ
PG
GND
V
IN
V
IN
DNC
ENABLE
SS
EPAD
Pin Descriptions
PIN
NUMBER
PIN
NAME DESCRIPTION
1, 2 V
OUT
Output voltage pin
3SENSE/
ADJ
Remote voltage sense for internally fixed V
OUT
options. ADJ pin for externally set V
OUT
.
4PGV
OUT
in regulation signal. Logic low defines when
V
OUT
is not in regulation. Must be grounded if not
used.
5GNDGND pin
6 SS External cap adjusts inrush current. Leave this pin
open if not used.
7ENABLE V
IN
independent chip enable. TTL and CMOS
compatible.
8 DNC Do not connect this pin to ground or supply. Leave
floating.
9, 10 V
IN
Input supply pin
EPAD EPAD must be connected to copper plane with as
many vias as possible for proper electrical and
optimal thermal performance.