www.latticesemi.com 1 DS1011_01.7
June 2012 Data Sheet DS1011
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
Features
Power-Down Mode I
CC
< 10µA
Programmable Threshold Monitors
• Simultaneously monitors up to six power supplies
• Programmable analog trip points (1% step size;
192 steps)
• Programmable glitch filter
• Power-off detection (75mV)
Embedded Programmable Timers
• Four independent timers
• 32µs to 2 second intervals for timing sequences
Embedded PLD for Logical Control
• Rugged 16-macrocell CPLD architecture
• 81 product terms / 28 inputs
• Implements state machines and combinatoria
l
fu
nctions
Digital I/O
• Two dedicated digital inputs
• Five programmable digital I/O pins
Two High-Voltage FET Drivers
• Power supply ramp up/down control
• Independently configurable for FET control or
d
igital output
Wide Supply Range (2.64V to 3.96V)
• In-system programmable through JTAG
• Industrial temperature range: -40°C to +85°C
• 24-pin and 32-pin QFNS packages, lead-fr
ee
op
tion
Description
The Power Manager II ispPAC-POWR607 is a general-
purpose power-supply monitor, reset generator and
watchdog timer, incorporating both in-system program-
mable logic and analog functions implemented in non-
volatile E
2
CMOS
®
technology. The ispPAC-POWR607
device provides six independent analog input channels
to monitor power supply voltages. Two general-purpose
digital inputs are also provided for miscellaneous control
functions.
The ispPAC-POWR607 provides up to seven open-drain
digital outputs that can be used for controlling DC-DC
converters, low-drop-out regulators (LDOs) and opto-
couplers, as well as for supervisory and general-pur-
pose logic interface functions. Two of these outputs
(HVOUT1-HVOUT2) can be configured as high-voltage
MOSFET drivers. In high-voltage mode these outputs
provide 9V for driving the gates of n-channel MOSFETs
used as high-side power switches to control power sup-
ply ramp up and ramp down rate. The remaining five
digital, open drain outputs can optionally be configured
as digital inputs to sense more input signals as needed,
such as manual reset, etc.
The diagram above shows how a ispPAC-POWR607 is
used in a typical application. It controls power to the
microprocessor system, generates the CPU reset and
monitors critical power supply voltages, generating
interrupts whenever faults are detected. It also provides
a watchdog timer function to detect CPU operating and
bus timeout errors.
The ispPAC-POWR607 incorporates a 16-macrocell
CPLD. Figure 1 shows the analog input comparators
and digital inputs used as inputs to the CPLD array. The
digital output pins providing the external control signals
are driven by the CPLD. Four independently program-
Application Block Diagram
Voltage Supervisor
ispPAC-POWR607
Reset Generator
Watchdog Timer
Power Down
DC-DC
#1
DC-DC
#2
DC-DC
#n
MOSFET Drivers (2)
Input Power Supply
On/Off
Power Up/Down Control
Power
Supply
Bus
CPU /
uProcessor
Interrupt –
Power Fail
CPU_Reset_in
WDT Trigger
Interrupt – WDT
Manual
Reset In
ispPAC-POWR607
In-System Programmable Power Supply Supervisor,
Reset Generator and Watchdog Timer
®
ispPAC-POWR607 Data Sheet
2
mable timers also interface with the CPLD and can create delays and time-outs ranging from 32µs to 2 seconds.
The CPLD is programmed using LogiBuilder™, an easy-to-learn language integrated into the PAC-Designer
®
soft-
ware. Control sequences are written to monitor the status of any of the analog input channel comparators or the
digital inputs.
Figure 1. ispPAC-POWR607 Block Diagram
Pin Descriptions
24-Pin QFNS
Pin Number
32-Pin QFNS
Pin Number Pin Name Pin Type Voltage Range Description
8, 9 11, 12 GND Ground Ground Ground
1
23 30 HVOUT1
Open Drain Output
2
0V to 10V Open-Drain Output 1
FET Gate Driver 0V to 9V High-voltage FET Gate Driver 1
24 31 HVOUT2
Open Drain Output
2
0V to 10V Open-Drain Output 2
FET Gate Driver 0V to 9V High-voltage FET Gate Driver 2
20 27 IN_OUT3
Digital Input
9
0V to 5.5V
PLD Input 3
Open Drain Output
2
Open Drain Output 3
19 26 IN_OUT4
Digital Input
9
0V to 5.5V
PLD Input 4
Open Drain Output
2
Open Drain Output 4
18 23 IN_OUT5
Digital Input
9
0V to 5.5V
PLD Input 5
Open Drain Output
2
Open Drain Output 5
17 22 IN_OUT6
Digital Input
9
0V to 5.5V
PLD Input 6
Open Drain Output
2
Open Drain Output 6
15 20 IN_OUT7
Digital Input
9
0V to 5.5V
PLD Input 7
Open Drain Output
2
Open Drain Output 7
22 29 IN1_PWRDN
Digital Input
10
0V to 5.5V
3
PLD Logic Input 1.
4, 5
When not used,
this pin should be pulled down with a
10k resistor.
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
IN1_PWRDN
IN2
VCC
HVOUT1
HVOUT2
IN_OUT3
IN_OUT4
IN_OUT5
IN_OUT6
IN_OUT7
TMS
TCK
TDI
TDO
VCCJ
GND
PLD
16 Macrocells
28 Inputs
JTAG Interface
6 Analog Voltage
Monitor Inputs
Power Down
Logic
4 Timers
ispPAC-POWR607