www.latticesemi.com 1 DS1015_01.8
September 2012 Data Sheet DS1015
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
Features
Monitor, Control, and Margin Multiple
Power Supplies
• Simultaneously monitors up to 12 power
supplies
• Provides up to 20 output control signals
• Provides up to eight analog outputs for
margining/trimming power supply voltages
• Programmable digital and analog circuitry
Power Supply Margin and Trim Functions
• Trim and margin up to eight power supplies
• Dynamic voltage control through I
2
C
• Four hardware selectable voltage profiles
• Independent Digital Closed-Loop Trim function
for
each output
Embedded PLD for Sequence Control
• 48-macrocell CPLD implements both state
machines and combinatorial logic functions
Embedded Programmable Timers
• Four independent timers
• 32µs to 2 second intervals for timing sequences
Analog Input Monitoring
• 12 independent analog monitor inputs
• Differential inputs for remote ground sense
• Two programmable threshold comparators per
analog input
• Hardware window comparison
• 10-bit ADC for I
2
C monitoring
High-Voltage FET Drivers
• Power supply ramp up/down control
• Programmable current and voltage output
• Independently configurable for FET control or
di
gital output
2-Wire (I
2
C/SMBus™ Compatible) Interface
• Comparator status monitor
• ADC readout
• Direct control of inputs and outputs
• Power sequence control
• Dynamic trimming/margining control
3.3V Operation, Wide Supply Range 2.8V to
3.96V
• In-system programmable through JTAG
• Industrial temperature range: -40°C to +85°C
• 100-pin TQFP package, lead-free option
Application Block Diagram
POL#1
POL#N
nigraM/mirT
CPU
ispPAC-POWR1220AT8
Signals
4 Timers
ADC
6 Digital
Inputs
I
2
C
Interface
I
2
C
Bus
Power Supply
Margin/Trim
Control Block
12 Analog Inputs
and Voltage Monitors
Digital Monitoring
Other Board Circuitry
Voltage
Monitoring
Enables
8 Analog
Trim
Outputs
Primary
Supply
Primary
Supply
Primary
Supply
Primary
Supply
Primary
Supply
16 Digital
Outputs
Other Control/Supervisory
CPLD
48 Macrocells
83 Inputs
4 MOSFET
Drivers
3.3V
2.5V
1.8V
Description
The Lattice Power Manager II ispPAC-POWR1220AT8
is a general-purpose power-supply monitor, sequence
and margin controller, incorporating both in-system pro-
grammable logic and in-system programmable analog
functions implemented in non-volatile E
2
CMOS
®
tech-
nology. The ispPAC-POWR1220AT8 device provides 12
independent analog input channels to monitor up to 12
power supply test points. Each of these input channels
offers a differential input to support remote ground
sensing, and has two independently programmable
comparators to support both high/low and in-bounds/
out-of-bounds (window-compare) monitor functions. Six
general-purpose digital inputs are also provided for mis-
cellaneous control functions.
The ispPAC-POWR1220AT8 provides 20 open-drain
digital outputs that can be used for controlling DC-DC
converters, low-drop-out regulators (LDOs) and opto-
couplers, as well as for supervisory and general-pur-
pose logic interface functions. Four of these outputs
ispPAC-POWR1220AT8
In-System Programmable Power Supply
Monitoring, Sequencing and Margining Controller
®
ispPAC-POWR1220AT8 Data Sheet
2
(HVOUT1-HVOUT4) may be configured as high-voltage MOSFET drivers. In high-voltage mode these outputs can
provide up to 12V for driving the gates of n-channel MOSFETs so that they can be used as high-side power
switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down.
The ispPAC-POWR1220AT8 incorporates a 48-macrocell CPLD that can be used to implement complex state
machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status
of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as
inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable
timers can create delays and time-outs ranging from 32µs to 2 seconds. The CPLD is programmed using Logi-
Builder™, an easy-to-learn language integrated into the PAC-Designer
®
software. Control sequences are written to
monitor the status of any of the analog input channel comparators or the digital inputs.
In addition to the sequence control functions, the ispPAC-POWR1220AT8 incorporates eight DACs for generating
trimming voltage to control the output voltage of a DC-DC converter. The trimming voltage can be set to four hard-
ware selectable preset values (voltage profiles) or can be dynamically loaded in to the DAC through the I
2
C bus.
Additionally, each power supply output voltage can be maintained typically within 0.5% tolerance across various
load conditions using the Digital Closed Loop Control mode. The operating voltage profile can either be selected
using external hardware pins or through the PLD outputs.
The on-chip 10-bit A/D converter can both be used to monitor the V
MON
voltage through the I
2
C bus as well as for
implementing digital closed loop mode for maintaining the output voltage of all power supplies controlled by the
monitoring and trimming section of the ispPAC-POWR1220AT8 device.
The I
2
C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the V
MON
inputs, read back the status of each of the V
MON
comparator and PLD outputs, control logic signals IN2 to IN5, con-
trol the output pins, and load the DACs for the generation of the trimming voltage of the external DC-DC converter.
Figure 1. ispPAC-POWR1220AT8 Block Diagram
CPLD
48 MACROCELLS
83 INPUTS
JTAG LOGIC
CLOCK
OSCILLATOR
TIMERS
(4)
I
2
C
INTERFACE
ADC
DAC
DAC
DAC
DAC
DAC
MARGIN/TRIM
CONTROL LOGIC
L
A
T
I
G
I
D
6
S
T U
P
N
I
S T U
P
N
I
G
O
L
A
N
A
2
1
S
R
O
T
I
N O M
E G
A
T
L
O
V
D
N
A
T
E
F
4
S
R E
V
I
R
D
N
I A
R
D
-
N
E
P
O
6
1
S
T
U
P
T U
O
L A
T I
G I D
VOLTAGE OUTPUT
DACS (8)
G N I
T
U
O
R
T
U
P
T
U
O
L
O
O
P
VMON1+
VMON1GS
VMON2+
VMON2GS
VMON3+
VMON3GS
VMON4+
VMON4GS
VMON5+
VMON5GS
VMON6+
VMON6GS
VMON7+
VMON7GS
VMON8+
VMON8GS
VMON9+
VMON9GS
VMON10+
VMON10GS
VMON11+
VMON11GS
VMON12+
VMON12GS
VPS0
VPS1
IN1
IN2
IN3
IN4
IN5
IN6
OUT5/SMBA
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
OUT17
HVOUT1
OUT18
OUT19
OUT20
HVOUT2
HVOUT3
HVOUT4
TRIM1
TRIM2
TRIM3
TRIM4
TRIM5
TRIM6
TRIM7
TRIM8
J
C
C
V
O
D
T
S M
T
K
C
T
I
D
T
L
E
S
K
L
C D
L
P
I
D
T
I
D
T
A
K
L
C
M
L
C
S
A
D
S
b
T E S E
R
G
O
R
P
C
C
V
GNDD (6)
GNDA (2)
VCCA
VCCD (3)
VCCINP
DAC
DAC
DAC