www.latticesemi.com 2-1 DS1014_01.9
February 2012 Data Sheet DS1014
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
Features
Monitor and Control Multiple Power
Supplies
• Simultaneously monitors up to 10 power
supplies
• Provides up to 14 output control signals
• Programmable digital and analog circuitry
Embedded PLD for Sequence Control
• 24-macrocell CPLD implements both state
machines and combinatorial logic functions
Embedded Programmable Timers
• Four independent timers
• 32µs to 2 second intervals for timing sequences
Analog Input Monitoring
• 10 independent analog monitor inputs
• Two programmable threshold comparators per
analog input
• Hardware window comparison
• 10-bit ADC for I
2
C monitoring (ispPAC-
POWR1014A only)
High-Voltage FET Drivers
• Power supply ramp up/down control
• Programmable current and voltage output
• Independently configurable for FET control or
di
gital output
2-Wire (I
2
C/SMBus™ Compatible) Interface
• Comparator status monitor
• ADC readout
• Direct control of inputs and outputs
• Power sequence contro
l
•
Only available with ispPAC-POWR1014A
3.3V Operation, Wide Supply Range 2.8V to
3.96V
• Industrial temperature range: -40°C to +85°C
• 48-pin TQFP package, lead-free option
Multi-Function JTAG Interface
• In-system programming
• Access to all I
2
C registers
• Direct input control
Application Block Diagram
POL#1
POL#N
CPU
ispPAC-POWR1014A
Signals
4 Timers
ADC*
*ispPAC-POWR1014A only.
4 Digital
Inputs
I
2
C
Interface
I
2
C
Bus*
10 Analog Inputs
and Voltage Monitors
Digital Monitoring
Other Board Circuitry
Voltage
Monitoring
Enables
Primary
Supply
Primary
Supply
Primary
Supply
Primary
Supply
Primary
Supply
12 Digital
Outputs
Other Control/Supervisory
CPLD
24 Macrocells
53 Inputs
2 MOSFET
Drivers
3.3V
2.5V
1.8V
Description
Lattice’s Power Manager II ispPAC-POWR1014/A is a
general-purpose power-supply monitor and sequence
controller, incorporating both in-system programmable
logic and in-system programmable analog functions
implemented in non-volatile E
2
CMOS
®
technology. The
ispPAC-POWR1014/A device provides 10 independent
analog input channels to monitor up to 10 power supply
test points. Each of these input channels has two inde-
pendently programmable comparators to support both
high/low and in-bounds/out-of-bounds (window-com-
pare) monitor functions. Four general-purpose digital
inputs are also provided for miscellaneous control func-
tions.
The ispPAC-POWR1014/A provides 14 open-drain digi-
tal outputs that can be used for controlling DC-DC con-
verters, low-drop-out regulators (LDOs) and opto-
couplers, as well as for supervisory and general-pur-
pose logic interface functions. Two of these outputs
(HVOUT1-HVOUT2) may be configured as high-voltage
ispPAC-POWR1014/A
In-System Programmable Power Supply Supervisor,
Reset Generator and Sequencing Controller
®
ispPAC-POWR1014/A Data Sheet
2-2
MOSFET drivers. In high-voltage mode these outputs can provide up to 12V for driving the gates of n-channel
MOSFETs so that they can be used as high-side power switches controlling the supplies with a programmable
ramp rate for both ramp up and ramp down.
The ispPAC-POWR1014/A incorporates a 24-macrocell CPLD that can be used to implement complex state
machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status
of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as
inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable
timers can create delays and time-outs ranging from 32µs to 2 seconds. The CPLD is programmed using Logi-
Builder™, an easy-to-learn language integrated into the PAC-Designer
®
software. Control sequences are written to
monitor the status of any of the analog input channel comparators or the digital inputs.
The on-chip 10-bit A/D converter is used to monitor the V
MON
voltage through the I
2
C bus or JTAG interface of the
ispPAC-POWR1014A device.
The I
2
C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the V
MON
inputs, read back the status of each of the V
MON
comparator and PLD outputs, control logic signals IN2 to IN4 and
control the output pins (ispPAC-POWR1014A only). The JTAG interface can be used to read out all I
2
C registers
during manufacturing.
Figure 2-1. ispPAC-POWR1014/A Block Diagram
CPLD
24 MACROCELLS
53 INPUTS
JTAG LOGIC
CLOCK
OSCILLATOR
TIMERS
(4)
I
2
C
INTERFACE
ADC*
MEASUREMENT
CONTROL LOGIC*
*ispPAC-POWR1014A only.
L
A
T
I
G
I
D
4
S
TU
P
N
I
STU
P
N
I
G
O
L
A
N
A
0
1
S
R
O
T
I
NOM
EG
A
T
L
O
V
D
N
A
T
E
F
2
S
RE
V
I
R
D
N
IA
R
D
-
N
E
P
O
2
1
S
T
U
P
TU
O
LA
TI
GID
GNI
T
U
O
R
T
U
P
T
U
O
L
O
O
P
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
IN1
IN2
IN3
IN4
OUT3/(SMBA*)
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
HVOUT1
HVOUT2
J
C
C
V
O
D
T
SM
T
K
C
T
TDISEL
K
L
CD
L
P
I
D
T
I
D
T
A
K
L
C
M
SDA*
SCL*
b
TE
SE
R
G
O
R
P
C
C
V
GNDD (2)
GNDA
VCCA
VCCD (2)
VCCINP