www.latticesemi.com 1 DS1022_01.7

ispMACH

4000ZE Family

1.8V In-System Programmable

Ultra Low Power PLDs

February 2012 Data Sheet DS1022

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Features

 High Performance

•f

MAX

= 260MHz maximum operating frequency

•t

= 4.4ns propagation delay

•

Up to four global clock pins with programmable

clock polarity control

• Up to 80 PTs per output

 Ease of Design

• Flexible CPLD macrocells with individual clock,

reset, preset and clock enable controls

• Up to four global OE controls

• Individual local OE control per I/O pin

• Excellent First-Time-Fit

and refit

• Wide input gating (36 input logic blocks) for fast

counters, state machines and address decoders

 Ultra Low Power

• Standby current as low as 10µA typical

• 1.8V core; low dynamic power

• Operational down to 1.6V V

• Superior solution for power sensitive consumer

applications

• Per pin pull-up, pull-down or bus keeper

control*

• Power Guard with multiple enable signals*

 Broad Device Offering

• 32 to 256 macrocells

• Multiple temperature range support

– Comme

rcial: 0 to 90°C junction (T

)

– I

ndustrial: -40 to 105°C junction (T

)

• Space-saving ucBGA and csBGA packages*

 Easy System Integration

• Operation with 3.3V, 2.5V, 1.8V or 1.5V

LVCMOS I/O

• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PC

int

erfaces

• Hot-socketing support

• Open-drain output option

• Programmable output slew rate

• 3.3V PCI compatible

• I/O pins with fast setup path

• Input hysteresis*

• 1.8V core power supply

• IEEE 1149.1 boundary scan testable

• IEEE 1532 ISC compliant

• 1.8V In-System Programmable (ISP™) us

ing

Boundar

y Scan Test Access Port (TAP)

• Pb-free package options (only)

• On-chip user oscillator and timer*

*New enhanced features over original ispMACH 4000Z

Table 1. ispMACH 4000ZE Family Selection Guide

ispMACH 4032ZE ispMACH 4064ZE ispMACH 4128ZE ispMACH 4256ZE

Macrocells 32 64 128 256

(ns) 4.4 4.7 5.8 5.8

(ns) 2.2 2.5 2.9 2.9

(ns) 3.0 3.2 3.8 3.8

MAX

(MHz) 260 241 200 200

Supply Voltages (V) 1.8V 1.8V 1.8V 1.8V

Packages

(I/O + Dedicated Inputs)

48-Pin TQFP (7 x 7mm) 32+4 32+4

64-Ball csBGA (5 x 5mm) 32+4 48+4

64-Ball ucBGA (4 x 4mm) 48+4

100-Pin TQFP (14 x 14mm) 64+10 64+10 64+10

132-Ball ucBGA (6 x 6mm) 96+4

144-Pin TQFP (20 x 20mm) 96+4 96+14

144-Ball csBGA (7 x 7mm) 64+10 96+4 108+4

1. Pb-free only.

ispMACH 4000ZE Family Data Sheet

Introduction

The high performance ispMACH 4000ZE family from Lattice offers an ultra low power CPLD solution. The new fam-

ily is based on Lattice’s industry-leading ispMACH 4000 architecture. Retaining the best of the previous generation,

the ispMACH 4000ZE architecture focuses on significant innovations to combine high performance with low power

in a flexible CPLD family. For example, the family’s new Power Guard feature minimizes dynamic power consump-

tion by preventing internal logic toggling due to unnecessary I/O pin activity.

The ispMACH 4000ZE combines high speed and low power with the flexibility needed for ease of design. With its

robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil-

ity, routing, pin-out retention and density migration.

The ispMACH 4000ZE family offers densities ranging from 32 to 256 macrocells. There are multiple density-I/O

combinations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA), and Ultra Chip Scale BGA (ucBGA) pack-

ages ranging from 32 to 144 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key

parameters.

A user programmable internal oscillator and a timer are included in the device for tasks like LED control, keyboard

scanner and similar housekeeping type state machines. This feature can be optionally disabled to save power.

The ispMACH 4000ZE family has enhanced system integration capabilities. It supports a 1.8V supply voltage and

3.3V, 2.5V, 1.8V and 1.5V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank

is configured for 3.3V operation, making this family 5V tolerant. The ispMACH 4000ZE also offers enhanced I/O

features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors,

open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a “per-pin”

basis. The ispMACH 4000ZE family members are 1.8V in-system programmable through the IEEE Standard 1532

interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test

equipment. The 1532 interface signals TCK, TMS, TDI and TDO are referenced to V

(logic core).

Overview

The ispMACH 4000ZE devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) intercon-

nected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs),

which contain multiple I/O cells. This architecture is shown in Figure 1.

Figure 1. Functional Block Diagram

I/O

Block

ORP ORP

OSC

GOE0

GOE1

GND

TCK

TMS

TDI

TDO

Generic

Logic

Block

Generic

Logic

Block

I/O

Block

ORP ORP

Generic

Logic

Block

Generic

Logic

Block

I/O

Block

I/O Bank 0

I/O Bank 1

I/O

Block

CLK0/I

CLK1/I

CLK2/I

CLK3/I

Global Routing Pool

CCO0

GND

CCO1

GND

16 16