Si3000PPT-EVB

EVALUATION BOARD FOR THE Si3000 WITH THE 

PARALLEL PORT INTERFACE

Description

The Si3000PPT-EVB provides the audio system

engineer an easy way to evaluate the functionality of

Silicon Laboratories’ Si3000 voice band codec solution.

The Si3000 chipset can be easily controlled from a PC

using the supplied application software (requires

Si30xxPPT software Rev 2.1 or above and FPGA Rev

2.1 or above).

Features

The Si3000PPT-EVB includes the following:

 Ability to read and write registers

 DAC waveform generation from a series of standard

waveforms or from a .wav file

 ADC data capture and display in either time or

frequency domain

 Recommended layout for key components

 Daisy-chain support when used with Si30xx (Si3034,

Si3035, Si3044, or Si3056) products

 RJ-11 Interface to Handset

 RJ-11 Connection to Phone Line and Modem

 Microphone, Speaker Interfaces

 Line In, Line out Interfaces

Functional Block Diagram

Motherboard

FPGA Si3000

Handset

Select

Line

Out

Phone Line

Handset

Daughtercard

Speaker

Out

Mic

SSI

PPT

Line Level

Audio I/O

12 V

Si3000PPT-EVB

2 Rev. 0.1

Functional Description

The Si3000PPT-EVB provides the audio system

engineer an easy way to evaluate the Si3000 voice

band codec solution.

The Si3000PPT-EVB also supports

the connection of

multiple devices on an SSI interface. The evaluation

board provides a straightforward means of evaluating

this feature.

The evaluation board consist

of the Si30xxPPT-EVB

motherboard and the Si3000DC_EVB daughter card. A

custom ribbon cable is also provided to connect to the

parallel port of a PC. Contact a Silicon Laboratories

representative for more information.

In this document, the Si3000DC-EVB is occasionally

ferred to as the “daughter card” and the Si30xxPPT-

EVB as the “motherboard”. The Si3000PPT-EVB refers

to the system which consists of both the “motherboard”

and “daughter card”.

Motherboard–Daughter Card Connection

The Si3000DC-EVB connects to the Si30xxPPT-EVB

through two sockets: JP1 and JP2. JP1 is a 3x8 socket

connection to the digital signals of the DSP-side chip. In

addition, a 3.3 V regulated supply is routed to this

socket

nd supplies the power to the digital-side device.

JP1 of the daughter card connects to JP2 of the

Si30xxPPT-EVB. JP2 is a 2x5 socket connection from

the TIP and RING and chassis ground of the line

interface to the line-side device. JP2 of the Si3000DC-

EVB connects to JP1 of the Si30xx PPT EVB.

Power Supply

Power is supplied to the EVB by means of J3 or J4. J3

is a euroblock header that allows for connection to a

bench power supply. J4 is a 2.1 mm power jack that

allows the use of

a wall transformer. A 9 V supply/

300 mA is

typically used, but the onboard voltage

gulator also works with a dc voltage between 7.5 V

and 2

0 V. A diode bridge is used to correct polarity. The

-board regulator, U7, provides 5 V to the call progress

circuit, the on-board oscillator, and other boards daisy

chained to the Si30xxPPT-EVB. This 5 V is further

lated to 3.3 V to power the daughter card and the

input/output port

s of the FPGA. A third regulator

provides 2.5 V for the core voltage of the FPGA.

Clock Generation

The Si3000 requires an MCLK input. An on-board

oscillator (Y1) is used by the FPGA to clock all the

subsystems as well as generate and provide the master

clock to the Si3000. The FPGA is designed to use a

18.432 MHz oscillator (included with the board).

Optional Call Progress Speaker

This feature is not utilized by the Si3000

Reset Circuit

The Si3000 requires an active low pulse on RESET

following powerup and whenever all registers need to

be reset. For development purposes, the Si3000PPT-

EVB includes a reset push button, SW1, that is used by

the FPGA to generate the reset pulse of the Si3000.

If multiple boards are cascaded together, the reset

sign

al sh

ould be generated by the master board. Using

the SW1 pushbutton on slave boards does not reset

that slave board.

Serial Modes

The Si3000 supports several different serial modes for a

glueless interface to many standard DSP and ASIC

serial ports. The serial mode of the Si3000 can be

selected by JP3 and JP4 on the motherboard.

Line Connection

The Si3000PPT-EVB has a physical interfaces

designed to connect to the phone line. It is on the

daughter card. These interfaces are equivalent and

interchangeable. When using the Si3000PPT-EVB in

slave mode, one of the line interfaces is used to connect

to the phone line, while the other line interface is used to

connect to the Master Board Modem Line Interface.

This way, both the Si3000PPT-EVB and Si30xxPPT-

EVB gain access to the phone line without requiring an

external phone splitter.

Handset Interface

The Si3000PPT-EVB includes a handset interface. This

interface is located on the daughter card J1 connector

pins 9 and 10.

A handset can connect directly to the phone line or the

the Si3000

device. The target system is expected to

control the DPDT relay to select the handset

connection. When the handset is connected to the

Si3000, both the Si3000 and handset are disconnected

from the phone line. In this case, the Si3000PPT-EVB

supplies dc power to the handset through an external

12 Vdc bench supply. The euroblock header, J6, on the

hter card is provided for this connection. 24.5 mA

of DC loop

current is supplied to the handset.

In a voice modem application, the Si3000PPT-EVB is

configured in the slave mode, with an

Si30xxPPT-EVB

acting as the master board. When this system is in the

on-hook state, either the Si30xx or the handset can

respond to the phone ring and place the system in the

off-hook state.