Rev 2.0, May 12, 2008 Page 1 of 12
400 West Cesar Chavez, Austin, TX 78701 1 (512) 416-8500 1 (512) 416-9669 www.silabs.com
SL2309
Not Recommended for New Designs
Key Features
10 to 140 MHz operating frequency range
Low output clock jitter:
140 ps-max cycle-to-cycle jitter
Low output-to-output skew: 150 ps-max
Low product-to-product skew: 400 ps-max
3.3 V power supply range
Low power dissipation:
26 mA-max at 66 MHz
44 mA –max at 133 MHz
One input drives 9 outputs organized as 4+4+1
Select mode to bypass PLL or tri-state outputs
SpreadThru™ PLL that allows use of SSCG
Standard and High-Drive options
Available in 16-pin SOIC and TSSOP packages
Available in Commercial and Industrial grades
Applications
Printers and MFPs
Digital Copiers
PCs and Work Stations
DTV
Routers, Switchers and Servers
Digital Embeded Systems
Description
The SL2309 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to nine (9)
clock outputs from one (1) reference input clock, for high
speed clock distribution applications.
The product has an on-chip PLL which locks to the input
clock at CLKIN and receives its feedback internally from
the CLKOUT pin.
The SL2309 has two (2) clock driver banks each with four
(4) clock outputs. These outputs are controlled by two (2)
select input pins S1 and S2. When only four (4) outputs
are needed, four (4) bank-B output clock buffers can be tri-
stated to reduce power dissipation and jitter. The select
inputs can also be used to tri-state both banks A and B or
drive them directly from the input bypassing the PLL and
making the product behave like a Non-Zero Delay Fanout
Buffer (NZDB).
The high-drive (-1H) version operates up to 140MHz and
low drive (-1) version operates up to 100MHz at 3.3V.
Benefits
Up to nine (9) distribution of input clock
Standard and High-Drive levels to control impedance
level, frequency range and EMI
Low power dissipation, jitter and skew
Low cost
Block Diagram
Low Power and
Low Jitter
PLL
MUX
Input Selection
Decoding Logic
VDD
GND
2
2
S2
S1
CLKIN
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)
Not Recommended
for New Designs
Rev 2.0, May 12, 2008 Page 2 of 12
SL2309
CLKA1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
CLKIN
CLKA2
VDD
GND
CLKB1
CLKB2
S2
Pin Description
Pin Configuration
16-Pin SOIC and TSSOP
Pin
Number
Pin Name
Pin Type
Pin Description
1
CLKIN
Input
Reference Frequency Clock Input. Weak pull-down (250kΩ).
2
CLKA1
Output
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
3
CLKA2
Output
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
4
VDD
Power
3.3V Power Supply.
5
GND
Power
Power Ground.
6
CLKB1
Output
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
7
CLKB2
Output
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
8
S2
Input
Select Input, select pin S2. Weak pull-up (250kΩ).
9
S1
Input
Select Input, select pin S1. Weak pull-up (250kΩ).
10
CLKB3
Output
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
11
CLKB4
Output
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
12
GND
Power
Power Ground.
13
VDD
Power
3.3V Power Supply.
14
CLKA3
Output
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
15
CLKA4
Output
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
16
CLKOUT
Output
Buffered Clock Output, PLL Internal Feedback Output. Weak pull-down (250kΩ).
Not Recommended
for New Designs