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MAX24405, MAX24410
5- or 10-Output Any-to-Any Clock Multipliers
General Description
The MAX24405 and MAX24410 are flexible, high-
performance clock multiplier/synthesizer ICs with two
independent APLLs. Each APLL performs any-to-any
frequency conversion. From any input clock frequency
9.72MHz to 750MHz these devices can produce
frequency-locked APLL output frequencies up to
750MHz and as many as 10 differential output clock
signals that are integer divisors of the APLL
frequencies. Output jitter is typically 0.18 to 0.3ps RMS
for an integer multiply and 0.25 to 0.4ps RMS for a
fractional multiply (12kHz to 20MHz). Each device can
configure itself from an external EEPROM so that clock
signals are available immediately after power-up or
reset.
Applications
Frequency conversion and synthesis applications in a
wide variety of equipment types
Ordering Information
PART
OUTPUTS
TEMP
RANGE
PIN-
PACKAGE
MAX24405EXG+
5
-40 to +85
81-CSBGA
MAX24410EXG+
10
-40 to +85
81-CSBGA
+Denotes a lead(Pb)-free/RoHS-compliant package.
Register Map appears on page 18.
Features
Input Clocks
One Crystal or CMOS Input
Three Differential or CMOS Inputs
Differential to 750MHz, CMOS to 160MHz
Clock Selection By Pin or Register Control
Two APLLs Plus 5 or 10 Output Clocks
APLLs Perform High Resolution Fractional-N
Clock Multiplication
Any Output Frequency from <1Hz to 750MHz
Each Output Has an Independent Divider
Output Jitter Typically 0.18 to 0.3ps RMS for
Integer Multiply and 0.25 to 0.4ps RMS for
Fractional Multiply (12kHz to 20MHz)
Outputs are CML or 2xCMOS, Can Interface to
LVDS, LVPECL, HSTL, SSTL and HCSL
CMOS Output Voltage from 1.5V to 3.3V
General Features
Automatic Self-Configuration at Power-Up
from External EEPROM Memory
SPI™ Processor Interface
1.8V + 3.3V Operation (5V Tolerant)
-40 to +85C Operating Temp. Range
Block Diagram
RST_N
CS_N
SCLK
SDI
SDO
GPIO1
TEST
IC1POS/NEG
IC2POS/NEG
OC1POS/NEG
DIV1
OC2POS/NEG
DIV2
OC3POS/NEG
DIV3
OC4POS/NEG
DIV4
OC5POS/NEG
DIV5
OC6POS/NEG
DIV6
OC7POS/NEG
DIV7
OC8POS/NEG
DIV8
OC9POS/NEG
DIV9
OC10POS/NEG
DIV10
IC3POS/NEG
XO
APLL1
3.7-4.2GHz,
Sub-ps jitter,
Fractional-N
Processor SPI Port
EEPROM SPI Port
and HW Control and Status Pins
GPIO2
AC / GPIO3
SS / GPIO4
INTREQ
XIN
XOUT
APLL2
3.7-4.2GHz,
Sub-ps jitter,
Fractional-N
JTAG
JTRST_N
JTMS
JTCLK
JTDI
JTDO
A
B
C
D
ECS_N
ESCLK
ESDI
ESDO
Data Sheet
November 2016
Figure 4-2
MAX24410 only
MAX24410 only
MAX24405, MAX24410
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Table of Contents
1. APPLICATION EXAMPLES .......................................................................................................... 4
2. DETAILED FEATURES ................................................................................................................. 5
2.1 APLL FEATURES .......................................................................................................................... 5
2.2 OUTPUT CLOCK FEATURES ........................................................................................................... 5
2.3 GENERAL FEATURES .................................................................................................................... 5
3. PIN DESCRIPTIONS ..................................................................................................................... 6
4. FUNCTIONAL DESCRIPTION ...................................................................................................... 9
4.1 DEVICE IDENTIFICATION AND PROTECTION ..................................................................................... 9
4.2 LOCAL OSCILLATOR OR CRYSTAL .................................................................................................. 9
4.2.1 External Oscillator ...................................................................................................................................9
4.2.2 On-Chip Crystal Oscillator ......................................................................................................................9
4.3 INPUT SIGNAL FORMAT CONFIGURATION .......................................................................................10
4.4 APLL CONFIGURATION ................................................................................................................11
4.4.1 Input Selection and Frequency ............................................................................................................ 11
4.4.2 Output Frequency ................................................................................................................................ 11
4.5 OUTPUT CLOCK CONFIGURATION .................................................................................................12
4.5.1 Enable, Signal Format, Voltage and Interfacing .................................................................................. 12
4.5.2 Frequency Configuration ...................................................................................................................... 13
4.5.3 Phase Adjustment ................................................................................................................................ 13
4.6 MICROPROCESSOR INTERFACE ....................................................................................................14
4.7 RESET LOGIC ..............................................................................................................................16
4.8 POWER-SUPPLY CONSIDERATIONS...............................................................................................16
4.9 INITIALIZATION AND EEPROM CONFIGURATION MEMORY ..............................................................16
5. REGISTER DESCRIPTIONS ........................................................................................................17
5.1 REGISTER TYPES ........................................................................................................................17
5.1.1 Status Bits ............................................................................................................................................ 17
5.1.2 Configuration Fields ............................................................................................................................. 17
5.1.3 Bank-Switched Registers ..................................................................................................................... 17
5.2 REGISTER MAP ................................................................ ...........................................................18
5.3 REGISTER DEFINITIONS ...............................................................................................................19
5.3.1 Global Registers ................................................................................................................................... 19
5.3.2 GPIO Registers .................................................................................................................................... 24
5.3.3 APLL Registers .................................................................................................................................... 27
5.3.4 Output Clock Registers ........................................................................................................................ 33
6. JTAG AND BOUNDARY SCAN ................................................................ ...................................37
6.1 JTAG DESCRIPTION ....................................................................................................................37
6.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION ..............................................................38
6.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS .......................................................................40
6.4 JTAG TEST REGISTERS ...............................................................................................................41
7. ELECTRICAL CHARACTERISTICS ............................................................................................42
8. PIN ASSIGNMENTS.....................................................................................................................51
8.1 MAX24405 PIN ASSSIGNMENT ....................................................................................................51
8.2 MAX24410 PIN ASSSIGNMENT ....................................................................................................53
9. PACKAGE AND THERMAL INFORMATION ...............................................................................55
9.1 PACKAGE TOP MARK FORMAT......................................................................................................55
9.2 THERMAL SPECIFICATIONS ...........................................................................................................56