Analog Dialogue 50-01, January 2016

An Engineering Walk Through

Virtual Eval

ADI’s Online Data Converter Product

Evaluation Tool

By Tom MacLeod and Jason Cockrell

Overview

Setting down your third cup of coffee, you pick up a pile of

specifications with a sigh. Today you face a familiar challenge:

Develop a next-generation platform that meets cutting-edge

requirements on an implausible timeline while remaining

within an unjustly slim budget, and do it all with a smile.

You must choose the right vendors for the project, and to

meet these ever more strenuous goals, you need vendors

that provide quality support alongside their core products.

Analog Devices rises to meet these expectations with such

support software as the Analog Filter Wizard and ADC

modeling tools. Now Analog Devices is taking the next step

with a comprehensive online product evaluation tool called

Virtual Eval. Virtual Eval employs detailed software models

to simulate crucial part performance characteristics without

the purchase of hardware. The overworked engineer can

configure a variety of operating conditions and device features

to establish custom use cases. The configuration settings are

dispatched to Analog Devices servers to kick off a simulation

job. Within seconds, the completed simulation results display

as graphs and performance metrics in the browser window.

Virtual Eval can solve a wide variety of design problems to

accelerate the product development cycle. The remainder of

this article covers two such problems out of many. In the first,

a data acquisition scenario, you must balance throughput rate

and noise performance to choose the right precision converter.

In the second, while working on a radio receiver, you need to

digitize some spectra with a minimum dynamic range require-

ment, while keeping overall system power low. In both cases,

Virtual Eval facilitates faster design decisions with greater

confidence through the use of online simulation.

Problem #1

Wading through the specification tome, the key requirements

slowly start to emerge:

• 4-channel signal acquisition, ±75 mV

• 18-bit performance or higher

• 50 Hz rejection below –40 dB

• Settling time of 50 ms, but faster is better

Spoiler alert! The Analog Devices AD7193 is the right part for

this job. The traditional method for making the correct part

selection is by utilizing the specifications in the product’s

data sheet to analyze the component’s performance under

various filtering and application conditions. There is a lot of

manual labor involved in this method and data sheets cannot

provide performance specifications for every possible combi-

nation of frequency selection and use case conditions of

analog.com/analogdialogue

interest to a wide variety of customers. What you really need

is an interactive tool like Virtual Eval to understand product

performance through custom simulations tailored to your

particular use case.

The first screen you see is the product chooser.

Figure 1. Product chooser.

Under Precision ADC, find the AD7193. One click loads the

evaluation session.

Figure 2. AD7193 functional block diagram.

The Functional Block Diagram view illustrates the layout

of the AD7193. Clickable components of the diagram reveal

the associated configurable settings in the accordion on the

left-hand side of the screen. Select the reference voltages and

observe a V

REF

of 2.5 V. Then, select the PGA component, and

change the PGA gain from 128 to 32, allowing for an analog

input range of ±2.5 V/32 = ±78.125 mV. This satisfies the ampli-

tude specification. Finally, click the Run button at the top of

the Settings column. Remote servers run a collection of simu-

lations, and deliver the performance results back to the Virtual

Eval client.

Analog Dialogue 50-01, January 2016

The rejection at 50 Hz is now about –41 dB, which satisfies

the specification. There is no way to determine this from the

data sheet, since Analog Devices does not publish the formu-

las used to compute frequency rejection. Only an interactive

simulation allows the engineer to directly verify product

performance in particular scenarios such as this.

Switching back to the Waveform view reveals that the settling

time is just 40.103 ms due to the reduction in filtering, easily

meeting the specifications.

Problem #2

Your company’s new platform must digitize approximately

50 MHz worth of spectrum located at 354 MHz with 72 dB of

signal-to-noise ratio. Fast forward to a design choice to use

an RF ADC, the AD9680. It has a sampling rate of 1 GSPS, an

on-chip digital downconverter, and a flexible JESD204B serial

interface. Its data sheet is very detailed and thorough, but as

mentioned previously, it just cannot possibly address every

potential use case. Virtual Eval can, so you open it from the

AD9680 product page.

Select the High Speed ADC category and click on the AD9680.

Figure 6. Product chooser.

You are presented with the default Virtual Eval session start-

ing with the Functional Block Diagram view:

Figure 7. AD9680 functional block diagram.

To interpret the results, switch to the Waveform view using

the tabs near the top of the screen.

Figure 3. Waveform view.

The Results column contains dependent variables computed

in the simulation, such as noise and power characteristics. The

peak-to-peak resolution is 18.531 bits, which satisfies the speci-

fications; however, the settling time of 80.103 ms does not.

In precision converters, this settling time is a function of

the filter configuration. Switching to the H(f) Response view

gives insight into the filtering performance of the product.

Figure 4. H(f) Response view.

The specifications require –40 dB of rejection at 50 Hz, but the

actual rejection power is –131 dB! That surplus of rejection

can be sacrificed to improve settling time. To dial back the

filtering, select the ADC element in the Settings column, and

change FS from 96 to 48. To ensure there is still a zero in the

filter response at 50 Hz, increase the Averaging from 1 to 2.

Lastly, change the sinc order from 4 to 3 to save a little more

settling time. Then run the simulation again.

Figure 5. H(f) response modified.