XAPP1205 (v1.0) March 28, 2014 www.xilinx.com 1

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Summary With high-end processing platforms such as the Xilinx Zynq®-7000 All Programmable SoC,

customers want to take full advantage of the processing system (PS) and custom peripherals

available within the device. An example of this philosophy is a system containing multiple video

pipelines in which live video streams are written into memory (input) and memory content is

sent out to live video streams (output) while the processor is accessing memory. This

application note covers design principles for obtaining high performance from the Zynq-7000

AP SoC memory interfaces, from AXI master interfaces implemented in the programmable

logic (PL), and from the ARM® Cortex™-A9 processor(s).

With video streams, guaranteed worst-case latency is required to ensure that frames are not

dropped or corrupted. To provide high-speed AXI interface masters in the PL with lower latency

and direct access to the Zynq-7000 AP SoC memory interfaces, connections to the High

Performance (HP) interfaces are required. The Zynq-7000 AP SoC contains four HP interfaces

that are 64-bit or 32-bit AXI3 slave interfaces designed for high throughput.

This design uses four AXI Video Direct Memory Access (VDMA) cores to simultaneously move

eight streams (four transmit video streams and four receive video streams), each in 1920 x

1080p format, 60 Hz refresh rate, and up to 24 data bits per pixel. Each AXI Video DMA core is

driven from a video test pattern generator (TPG) with a Video Timing Controller (VTC) core to

set up the necessary video timing signals. Data read by each AXI Video DMA core is sent to a

common Video On-Screen Display (OSD) core capable of multiplexing or overlaying multiple

video streams to a single output video stream. The onboard HDMI™ video display interface is

driven by the output of the Video On-Screen Display core with additional IP cores.

An AXI Performance Monitor core is used to capture performance data. All four AXI Video DMA

cores are connected to four separate HP interfaces using the AXI Interconnect and are

controlled by the Cortex-A9 processor. This design uses 70% of the memory controller

bandwidth.

The reference system design is targeted for the Zynq-7000 AP SoC ZC702 evaluation board.

Included

Systems

The design is built using the Vivado® Design Suite, System Edition 2013.4 and the Vivado IP

integrator feature. The IP integrator helps simplify the task of instantiating, configuring, and

connecting IP cores together to form complex integrated systems. The design also includes

software built using the Xilinx Software Development Kit (SDK). The software runs on the

Zynq-7000 AP SoC PS and implements the control function. The complete IP integrator project

and SDK tool project files are provided with this application note to allow the designer to

examine and rebuild this design or use the files as a template for starting a new design.

Included with this application note is one reference system, zc702_video_4x_ipi, available

in the ZIP file xapp1205-high-performance-video-zynq.zip. See the Reference

Design section.

Application Note: Zynq-7000 All Programmable SoC

XAPP1205 (v1.0) March 28, 2014

Designing High-Performance Video Systems

with the Zynq-7000 All Programmable SoC

Using IP Integrator

Author: James Lucero and Bob Slous

Introduction

XAPP1205 (v1.0) March 28, 2014 www.xilinx.com 2

Introduction High performance video systems can be created using available Xilinx LogiCORE™ IP AXI

Interface cores. Using AXI interconnect, AXI3 ports on the Zynq-7000 AP SoC, and AXI Video

DMA IP cores can form the basis of video systems capable of handling multiple video streams

and multiple video frame buffers sharing a common DDR3 SDRAM. AXI is a standardized IP

interface protocol based on the ARM AMBA4 and AMBA3 AXI specifications. The AXI

interfaces used in this example design consists of AXI4, AXI3, AXI4-Lite, and AXI4-Stream

interfaces as described in the AMBA4 and AMBA3 AXI specification [Ref 3]. These interfaces

provide a common IP interface protocol framework for building the design.

AXI interconnect and AXI HP ports on the Zynq-7000 AP SoC implement a high-bandwidth

multi-ported memory controller (MPMC) for use in applications where multiple devices share a

common memory controller. This configuration is a requirement in many video, embedded, and

communications applications where data from multiple sources move through a common

memory device, typically DDR3 SDRAM.

The AXI Video DMA core implements a high-performance video optimized DMA engine with

frame buffering, scatter gather (typically not used), and 2-Dimensional (2D) DMA features. The

AXI Video DMA core transfers video data streams to and from memory and operates under

dynamic software control or static configuration modes.

The Zynq-7000 AP SoC PS supplies clocks and resets throughout the system including the PL.

High-level control of the system is provided in the Zynq-7000 AP SoC PS by the Cortex-A9

processor and through the I/O peripherals (IOP), on-chip memory (OCM), and processor

support IP cores. To optimize the system to balance performance and area utilization, multiple

AXI interface cores are used to implement segmented/hierarchical AXI interface networks with

each AXI interface core individually tuned and optimized.

Hardware

Requirements

The hardware requirements for this reference system are:

• Xilinx ZC702 Rev C evaluation board (in JTAG mode)

• Two USB Type-A to Mini-B 5-pin cables

• HDMI cable

• Display monitor supporting 1080P resolution (1920x1080 resolution at 60 frames/sec)

The installed software tool requirements for building and downloading this reference system

are:

• Vivado Design Suite, System Edition 2013.4

• SDK 2013.4

Reference

System

Specifics

The reference system includes these LogiCORE IP cores:

• Processing System 7

• AXI Memory Interconnect (AXI_INTERCONNECT)

• Video Timing Controller (V_TC)

• Test Pattern Generator (V_TPG)

• AXI Video DMA (AXI_VDMA)

• AXI Performance Monitor (AXI_PERF_MON)

• Video On-Screen Display (V_OSD)

• AXI4-Stream to Video Out (AXI4S_VID_OUT)

• Chroma Resampler (V_CRESAMPLE)

• RGB to YCrCb Color-Space Converter (V_RGB2YCRCB)

The design also includes a clock generator and a custom core, ZYNQ_ADDR_SWITCH.