LATTICESEMI.COM
Leading-edge design and implementation tools optimized
for Lattice FPGA architectures
*Aldec Active-HDL Lattice Edition II simulator is only available for Windows.
Floating licenses require the additional ALDEC-USBKEY product.
ADVANCED DESIGN SOFTWARE
Key Features and Benefits
Design Exploration
• Explore design alternatives with Implementations & Strategies
• Run Manager for accelerating exploration and utilizing multi-
core processors
• Lattice Synthesis Engine (LSE) for additional synthesis
exploration options.
Ease-of-Use Features
• Advanced next generation user interface
• Report view with message ltering features
• Extensive cross-probing support
• File list View for managing multiple constraint, preference,
debug, timing analyzer, and power calculator les
• ECO Editor for specic physical netlist-level changes
• Platform Designer tool for mixed signal device applications
• Programmer for improved programming support
Improved Design Flow
• New Timing Analyzer view allows updated timing analysis,
including clock jitter analysis, without re-implementing the
design
• Simulation Wizard to easily export designs to multiple
simulators
Additional Software Included with Diamond
• LatticeMico™ system integration for embedded microprocessor
applications
• EPIC full-featured physical netlist-level editor
Lattice Diamond
®
design software offers leading-edge design and
implementation tools optimized for cost-sensitive, low-power Lattice
FPGA architectures. Diamond is the next generation replacement
for ispLEVER
®
featuring design exploration, ease of use, improved
design ow, and numerous other enhancements. This combination
of new and enhanced features allows users to complete designs
faster, easier and with better results than before.
Diamond software is available as a download from the Lattice
website for both Windows and Linux. Once downloaded and
installed, it can be used with either a free license or a subscription
license.
Diamond Software Free License
A free license can be downloaded from the Lattice website. This
license provides immediate access to many popular Lattice devices
such as ECP5U, MachXO3L™, MachXO2™, MachXO™, Platform
Manager 2, and LatticeXP2™ at no cost. It includes Synopsys
®
Synplify Pro™ for Lattice synthesis and Aldec
®
Active-HDL™
Lattice Edition II mixed language simulator.*
Diamond Software Subscription License
A subscription license provides support for all Lattice FPGAs
including ECP5UM and LatticeECP3 devices. It also includes
Synopsys
®
Synplify Pro™ for Lattice synthesis and Aldec Active-
HDL Lattice Edition II mixed language simulator*.
Lattice Diamond Key Features
Projects / Implementations/
Strategies
Diamond allows more robust projects
and offers new capabilities for improved
design exploration. Key features include:
Mixing of Verilog, VHDL, EDIF, and
schematic sources
Implementations allow multiple versions
of a design within a single project for
easy design exploration
Strategies allow implementation “recipes”
to be applied to any implementation within
a project or shared between projects
Manage and choose les for constraints,
timing analysis, power calculation, and
hardware debug
Ease of Use
Improved Design Flow
Use Run Manager view for parallel
processing of multiple implementations
to explore design alternatives for the
best results
HDL Analysis Tools
Hierarchy view automatically parses
and displays the design structure
Displays post-synthesis and post-map
design resources
Provides easy access to source les
for each hierarchy level
Options for hierarchy control, test bench
generation, and symbol generation
Key GUI Elements
Common menu and button locations
for all views
Three user interface sections for tools,
projects, and output
Start Page – open projects, import
ispLEVER projects, online help,
software updates
Report View – centralized location for
all reports from implementation tools
Add clock jitter analysis to improve the
robustness of your design
Scripting with Tcl
Tcl command dictionaries for projects,
netlists, HDL code checking, power
calculation, and hardware debug
In addition to the Tcl console in the
Diamond environment, a separate
Tcl console application allows running
scripts independently
Easy Export to Simulators
The new Simulation Wizard guides
you through all the necessary steps to
get your design to Aldec or ModelSim
simulators in the manner you choose.
Design Exploration
Speeding Common Functions
with ECO Editor & Programmer
ECO Editor provides easy editing of
common netlist changes without using
the EPIC full editor
Programmer allows easy and intuitive
programming of FPGAs
Deployment Tool creates a device
programming le format for the user’s
deployment method
GUI for a New
Generation of Tools
The Diamond user interface combines
leading edge features and customization
while offering improved ease of use.
All tools open in “Views” integrated into
a common user interface. Once the
operation for a single tool is learned, this
knowledge can be applied to other tools.
Fast, Easy Timing Analysis
Timing Analysis view offers an easy-to-
use graphical environment for navigating
timing information.
See timing, schematic, and detailed
paths for any constraint graphically
Easy visual cues provide instant design
feedback
Rapidly updated analysis when timing
constraints are changed
Synthesis Options
Lattice Synthesis Engine (LSE)
and Synplify Pro are available for
exploring to achieve best results.
LSE supports most families, while
Synplify Pro supports all families.
These two synthesis options support
Verilog and VHDL languages and use
Synopsys Design Constraints format for
constraints.