June 2020 United Silicon Carbide, Inc. 2
www.unitedsic.com
This report summarizes the JEDEC qualification results for the 650V UF3SC Discrete SiC
Cascodes in DFN8x8 surface mount plastic packages.
The environmental stress tests listed below are performed with pre-stress and post-
stress electrical tests. Reviewing the electrical results for new failures and any
significant shift in performance satisfies the qualification requirements.
Reliability Stress Test Summary
Test Name Test Standard
# Samples
x # Lots
Failures
High Temperature
Reverse Bias
(HTRB)
MIL-STD-750-1
M1038 Method A
(1000 Hours)
T
J
=150
o
C, V=80% V
max
77x3 lots 0/231
High Temperature
Gate Bias
(HTGB)
JESD22 A-108
(1000 Hours)
T
J
=150
o
C, V=100% V
max
(+25V), bias in
one direction
77x3 lots 0/231
MSL3 Pre-
Conditioning
JESD22-A113D
T
A
=30°C, RH = 60%,(192Hrs)
77 x 3 lots for
H3TRB, PCT,
and TC
& 30 x 1 lot
for RSH
0/723
High Humidity, High
Temperature Reverse
Bias
(H3TRB)
†
JESD22-A101C
(1000 Hours)
T
A
=85
o
C, 85% RH, V
GS
=0V, V
DS
=100V
77x3 lots 0/231
Temperature Cycle
(TC)
†
JESD22 A-104
(1000 Cycles)
77x3 lots 0/231
Autoclave
(PCT)
†
JESD22 A-102
121°C/ RH = 100%, 96 hours, 15psig
77x3 lots 0/231
Intermittent Operating
Life (IOL)
MIL-STD-750
Method 1037
ΔT
J
≥125ºC, 3000 cycles (5 minutes
on/ 5 minutes off)
77x3 lots 0/231