1©2020 Renesas Electronics Corporation February 25, 2020

Overview

The 8A34001 Synchronization Management Unit (SMU) provides

tools to manage timing references, clock sources, and timing

paths for IEEE 1588 and Synchronous Ethernet (SyncE) based

clocks. The PLL channels can act independently as frequency

synthesizers, jitter attenuators, Digitally Controlled Oscillators

(DCO), or Digital Phase Lock Loops (DPLL).

Optional clock recovery filter/servo software is available under

▪ Core and access IP switches/routers

▪ Synchronous Ethernet equipment

▪ Telecom Boundary Clocks (T-BCs) and Telecom Time Slave

Clocks (T-TSCs) according to ITU-T G.8273.2

▪ 10Gb, 40Gb, and 100Gb Ethernet interfaces

▪ Central Office Timing Source and Distribution

▪ Wireless infrastructure for 4.5G and 5G network equipment

▪ Eight independent timing channels

• Each can act as a frequency synthesizer, jitter attenuator,

• DPLL Digital Loop Filters (DLFs) are programmable with cut

off frequencies from 12µHz to 22kHz

• DPLL/DCO channels share frequency information using the

Combo Bus to simplify compliance with ITU-T G.8273.2

• Switching between DPLL and DCO modes is hitless and

▪ Automatic reference switching between DCO and DPLL

interface in a T-BC

• Generates output frequencies that are independent of input

• Differential output swing is selectable: 400mV / 650mV /

• Independent output voltages of 3.3V, 2.5V, or 1.8V

▪ LVCMOS additionally supports 1.5V or 1.2V

• The clock phase of each output is individually programmable

in 1ns to 2ns steps with a total range of ±180°

▪ 8 differential / 16 single-ended clock inputs

• Supports frequencies from 0.5Hz to 1GHz

• Any input can be mapped to any or all of the timing channels

1ps steps

▪ Reference monitors qualify/disqualify references depending on

LOS, activity, frequency monitoring, and/or LOS input pins

• Loss of Signal (LOS) input pins (via GPIOs) can be assigned

▪ Automatic reference selection state machines select the active

reference for each DPLL based on the reference monitors,

priority tables, revertive/non-revertive, and other

▪ System APLL operates from fundamental-mode crystal: 25MHz

-16

▪ DPLL Phase detectors can be used as Time-to-Digital

Converters (TDC) with precision below 1ps

▪ Supports 1MHz I

▪ Can configure itself automatically after reset via:

• Internal customer-programmable One-Time Programmable

(OTP) memory with up to 16 different configurations

2©2020 Renesas Electronics Corporation February 25, 2020

8A34001 Datasheet

The 8A34001 is a Synchronization Management Unit (SMU) for packet-based and physical layer based equipment synchronization. The

device is a highly integrated device that provides tools to manage timing references, clock sources and timing paths for IEEE 1588 and

Synchronous Ethernet (SyncE) based clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators,

The 8A34001 supports multiple independent timing paths that can each be configured as a DPLL or as a DCO. Input-to-input,

input-to-output, and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly