NXP Semiconductors

Data Sheet: Technical Data

Document Number: IMXRT1010CEC

Rev. 0, 09/2019

MIMXRT1011DAE5A

Package Information

Plastic Package

80-Pin LQFP, 12 x 12 mm, 0.5 mm pitch

Ordering Information

See Table 1 on page 4

NXP reserves the right to change the production detail specifications as may be required

to permit improvements in the design of its products.

1 i.MX RT1010 introduction

The i.MX RT1010 is a member of i.MX RT real-time

processor family based on the Arm

Cortex

-M7 core,

which operates at speeds up to 500 MHz to provide high

CPU performance and best real-time response.

The i.MX RT1010 processor has 128 KB on-chip RAM,

which can be flexibly configured as TCM or

general-purpose on-chip RAM. The i.MX RT1010

integrates advanced power management module with

DCDC and LDO that reduces complexity of external

power supply and simplifies power sequencing. The

i.MX RT1010 also provides various memory interfaces,

including Quad SPI, and a wide range of connectivity

interfaces, including UART, SPI, I2C, and USB; for

connecting peripherals including WLAN, Bluetooth™,

and GPS. The i.MX RT1010 also has rich audio features,

including SPDIF and I2S audio interface. Various analog

IP integration, including ADC, temperature sensor, and

etc.

i.MX RT1010 Crossover

Processors Data Sheet

for Consumer Products

1. i.MX RT1010 introduction . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 4

2. Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1. Special signal considerations . . . . . . . . . . . . . . . 12

3.2. Recommended connections for unused analog

interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 15

4.2. System power and clocks . . . . . . . . . . . . . . . . . . 21

4.3. I/O parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.4. System modules . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.5. External memory interface . . . . . . . . . . . . . . . . . 34

4.6. Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.7. Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.8. Communication interfaces . . . . . . . . . . . . . . . . . . 49

4.9. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 55

5.1. Boot mode configuration pins . . . . . . . . . . . . . . . 55

5.2. Boot device interface allocation . . . . . . . . . . . . . . 55

6. Package information and contact assignments . . . . . . . 57

6.1. 12 x 12 mm package information . . . . . . . . . . . . 57

7. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019

2 NXP Semiconductors

i.MX RT1010 introduction

The i.MX RT1010 is specifically useful for applications, such as:

• Audio

• Industrial

• Motor Control

• Home Appliance

•IoT

1.1 Features

The i.MX RT1010 processors are based on Arm Cortex-M7 MPCore™ Platform, which has the

following features:

• Supports single Arm

Cortex

-M7 with:

— 16 KB L1 Instruction Cache

— 8 KB L1 Data Cache

— Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture

— Support the Armv7-M Thumb instruction set, defined in the ARM v7-M architecture

• Integrated MPU, up to 16 individual protection regions

• Up to 128 KB I-TCM and D-TCM in total

• Up to 500 MHz frequency

• Cortex

M7 CoreSight™ components integration for debug

• Frequency of the core, as per Table 9, "Operating ranges," on page 16.

The SoC-level memory system consists of the following additional components:

— Boot ROM (64 KB)

— On-chip RAM (128 KB)

– Configurable RAM size up to 128 KB shared with CM7 TCM

• External memory interfaces:

— SPI NOR FLASH

— Single/Dual channel Quad SPI FLASH with XIP support and on-the-fly decryption

— Octal flash

• Timers and PWMs:

— Two General Programmable Timers (GPT)

– 4-channel generic 32-bit resolution timer for each

– Each support standard capture and compare operation

— Periodical Interrupt Timer (PIT)

– Generic 32-bit resolution timer

– Periodical interrupt generation

—FlexPWM

– Up to 4 submodules