AN114
Rev 0.2, 01-Nov-2018
I
nnovative Power
TM
ActiveSwitcher
TM
is a trademark of Active-Semi.
1
ACT88430 Register Definitions – CMI 101
Abstract
This application note identifies and explains the ACT88430 internal registers that help make this IC flexible and
configurable for many applications. It provides a short description of each register, its individual bits, their
function, and default values. This application note is specific to the Code Matrix Index, CMI 101.
Introduction
The ACT88430 is an ActivePMU power management unit from Active-Semi. It is designed to power a wide
range of processors, FPGA’s, peripherals, microcontroller and solid-state drive applications. The ACT88430
core includes 4 DC/DC step down converters using integrated power FETs and 3 low-dropout regulators (LDOs).
Each regulator can be configured for a wide range of output voltages through the I2C interface.
Today’s processors require more complexity in their startup and sequencing requirements. This is also true for
entering and exiting sleep and low power modes. The ACT88430 is specifically designed to meet today’s
processors’ stringent power system requirements. These processors include, but are not limited to
Atmel SAMA5D, SAMA9G (need updated compatible processors)
Rockchip RK2906, RK2918
Samsung S3C2416, S3C2440, S3C2450
Core Logic
Although the ACT88430 is programmed at the factory with a default configuration, these settings can be
changed through the I2C interface to provide customized configurations optimized for a specific processor
and/or end application. IC configurability includes many options such as output voltage, startup sequencing,
startup timing, slew rates, GPIO configuration, fault responses, and more. Active-Semi identifies these
configurations with a Code Matrix Index, CMI. An IC’s CMI is identified by the last three digits at the end of the
orderable part number. Note that this application note is specific to the ACT88430’s CMI 101. Refer to the
appropriate application note for register information for other CMI versions.
Register Types
The ACT88430 contains the following register types.
Basic Volatile - Customer R/W (Read and Write) and RO (Read only). The customer can modify these register
values to change IC functionality. Any changes to these registers are lost when power is recycled. The default
values are fixed and cannot be changed.
Basic Non-Volatile - Customer R/W and RO. The customer can modify these register values to change IC
functionality. Any changes to these registers are lost when power is recycled. The default values can be
modified at the factory to optimize IC functionality for specific applications. Please consult sales@active-
semi.com for custom options and minimum order quantities.
The ACT88430 contains seven major register spaces.
Master Reg 0x00h to 0x2Fh
Buck1 Reg 0x30h to 0x3Fh
Buck2 Reg 0x40h to 0x4Fh
Buck3 Reg 0x50h to 0x5Fh
Buck4 Reg 0x60h to 0x6Fh
LDO1 Reg 0x70h thru 0x7Fh
LDO23 Reg 0x80h thru 0x8Fh
Preliminary
AN-114
Rev 0.1, 09-Sep-2018
Innovative Power
TM
ActiveSwitcher
TM
is a trademark of Active-Semi.
2
REGISTER MAP
ADDR(HEX)
765432 1 0
0 nRESET_AUX1_MASK nRESET_AUX2_MASK nRST_MASK
RFU
POK_nMASK IRQ_nMASK DVS_EN PWREN_EN
1 RFU RFU RFU RFU RFU RFU SLP_ENTR IDLE_ENTR
2 CURRENT_STATE[2] CURRENT_STATE[1] CURRENT_STATE[0] PW REN_STAT TSD_SHUTDW N
TSD_ALERT
POK_OV POK_UV
3 RFU RFU RFU RFU RFU RFU GPIO_STAT MODE_STAT
4 RFU ILIM_REG[6] ILIM_REG[5] ILIM_REG[4] ILIM_REG[3] ILIM_REG[2] ILIM_REG[1] ILIM_REG[0]
5 RFU OV_REG[6] OV_REG[5] OV_REG[4] OV_REG[3] OV_REG[2] OV_REG[1] OV_REG[0]
6 RFU UV_REG[6] UV_REG[5] UV_REG[4] UV_REG[3] UV_REG[2] UV_REG[1] UV_REG[0]
7
8 nRST_DLY[2] nRST_DLY[1] nRST_DLY[0] POK_UV_SET[1] POK_UV_SET[0] EXT_EN_POL PWR_DN_MODE PWR_DN_POL
9 nRESET_AUX1_EN
L
DO2_nRESET_AUX1_E
N
nRESET_AUX1_DLY[2] nRESET_AUX1_DLY[1] nRESET_AUX1_DLY[0] nRESET_AUX2_DLY[2] nRESET_AUX2_DLY[1] nRESET_AUX2_DLY[0]
AEXT_PG_SEL
EN_B4_L3_PWRDN
VIN_OV_MASK TSD _nMASK UV_nMASK O V_nMASK nR ES ET_AUX1_PULLDOW N EXT_PG_POL
0
1E
PWR_GOOD OV ILIM RFU NRESET_FLTMSK ILIM_FLTMSK UV_FLTMSK OV_FLTMSK
1F
20
21
ON PBINEN QLTCH SLEEPEN DREN
22
MOD E R ST
23
24
PHASE_DELAY PHASE ForcePWM
25
2B
2C
TM ANALOG TMBRSTON TMLSON TMHSON
2D
TMMinOnBURST TM Isense TM FETdiv5 TM - Spare TM_EE_VT TM - Spare
TM - Spare
( Prog in MSTR)
EE_READ
40
PWR_GOOD OV ILIM RFU NRESET_FLTMSK ILIM_FLTMSK UV_FLTMSK OV_FLTMSK
41
42
43
ON PBINEN QLTCH SLEEPEN DREN
44
MOD E R ST
45
46
PHASE_DELAY PHASE ForcePWM
47
4D
4E
TM ANALOG TMBRSTON TMLSON TMHSON
4F
TMMi n ONBU RST TM Is ens e TM FE Tdiv5 TM - S p are TM_ EE_VT TM - Spare
TM - Spare
( Prog in MSTR)
EE_READ
50
PWR_GOOD OV ILIM RFU NRESET_FLTMSK ILIM_FLTMSK UV_FLTMSK OV_FLTMSK
51
52
53
ON PBINEN QLTCH SLEEPEN DREN
54
MOD E R ST
55
56
PHASE_DELAY PHASE ForcePWM
57
5D
5E
TM ANALOG TMBRSTON TMLSON TMHSON
5F
TMMi n ONBU RST TM Is ens e TM FE Tdiv5 TM - S p are TM_ EE_VT TM - Spare
TM - Spare
( Prog in MSTR)
EE_READ
60
PWR_GOOD OV ILIM RFU NRESET_FLTMSK ILIM_FLTMSK UV_FLTMSK OV_FLTMSK
61
62
63
ON PBINEN QLTCH SLEEPEN DREN
64
MOD E R ST
65
66
PHASE_DELAY PHASE ForcePWM
67
6D
70
PWR_GOOD_LDO1 OV_LDO1 ILIM_LDO1 RFU nRESET_FLTMSK ILIM_FLTMSK_LDO1 UV_FLTMSK_LDO1 OV_FLTMSK_LDO1
71
RFU
72
ON PBINEN QLTCH SLEEPEN/SCRATCH DREN SEL_REF0P8_BUCK2
73
MOD E R ST
74
SEL_REF0P8_BUCK1
75
76
LSW_MODE
77
78
RFURFURFURFURFURFU RFU RFU
79
7A
B3_lpm_load_step EN_PUSH_PULL_IO8
7B
B4_LSASYNC B3_LSASYNC B2_LSASYNC B1_LSASYNC B4_LP_MODE B3_LPMODE B2_LP_MODE B1_LP_MODE
7C
B4_HalfFreq B3_HalfFreq B2_HalfFreq B1_HalfFreq B4_DISPULLDOWN B3_DISPULLDOWN B2_DISPULLDOWN B1_DISPULLDOWN
7D
80
PWR_GOOD_LDO2 OV_LDO2 ILIM_LDO2 RFU RFU ILIM_FLTMSK_LDO2 UV_FLTMSK_LDO2 OV_FLTMSK_LDO2
81
RANGE_LDO2 RANGE_LDO3
82
ON PBINEN QLTCH SLEEPEN DREN B4_lpm_load_step
83
MOD E R ST
84
RFU
85
86
vin_full_range
87
88
PWR_GOOD_LDO3 OV_LDO3 ILIM_LDO3 RFU nRESET_FLTMSK_LDO23 ILIM_FLTMSK_LDO3 UV_FLTMSK_LDO3 OV_FLTMSK_LDO3
89
SEL_REF0P8_BUCK3 B1_lpm_load_step
8A
ON PBINEN QLTCH SLEEPEN DREN LDO3_SS_BIAS_INC
8B
MOD E R ST
8C
RFU
Master Registers
Buck1 Registers
Buck2 Registers
Buck4 Registers
LDO1 Registers
LDO2/3 Registers
LDO 3 VSET
SS_RAMP
DBQL DBOK
DBON ONDLY
DBON ONDLY
DO NOT USE
LDO 2 VSET
SS_RAMP
DBQL DBOK
B3_ILIM B4_ILIM
LDO1_ILIM LDO2_ILIM LDO3_ILIM
CMI_IDENTIFICATION
DBON ONDLY
DO NOT USE
DO NOT USE
LDO 1 VSET
SS_RAMP
DBQL DBOK
ONDLY DRVADJ
DO NOT USE
B234_VSET1
SS_RAMP
DBQL DBOK
DBON SLEW DBSTBY
DBON SLEW DBSTBY
ONDLY DRVADJ
DO NOT USE
DO NOT USE
TM
B234_VSET0
SLEW DBSTBY
ONDLY DRVADJ
DO NOT USE
DO NOT USE
SLEW DBSTBY
ONDLY
B1_ILIM B2_ILIM
DBOK
DO NOT USE
TM
B234_VSET0
Buck3 Registers
B234_VSET1
SS_RAMP
DBQL DBOK
SS_RAMP
DBQL DBOK
DBON
TM
B234_VSET0
B234_VSET1
DBON
DRVADJ
DO NOT USE
B1_VSET0
B1_VSET1
SS_RAMP
DBQL
RFU
Preliminary