DATASHEET
551S SEPTEMBER 20, 2018 1 ©2018 Integrated Device Technology, Inc.
Low Skew 1 to 4 Clock Buffer 551S
Description
The 551S is a low cost, high-speed single inp ut to four outp ut
clock buffer. The 551S has best in class Additive Phase Jitter
of sub 50fsec.
IDT makes many non-PLL and PLL based low skew output
devices as well as Zero Delay Buffers to synchronize clocks.
Contact IDT for all of your clocking needs.
Features
• Low additive phase jitter RMS: 50fs
• Extremely low skew outputs (50ps)
• Low cost clock buffer
• Packaged in 8-pin SOIC and 8-pin DFN, Pb-free
• Input/Output clock frequency up to 200MHz
• Non-inverting output clock
• Ideal for network i ng clock s
• Operating Volta ge s: 1.8V to 3.3V
• Output Enable mode tri-states ou tputs
• Advanced, low power CMOS process
• Extended temperature range (-40°C to +105°C)
Block Diagram
Q1
ICLK
Q2
Q3
Q4
Output Enable