Introduction

For next-generation designs, high-performance data converters and analog

front ends (AFEs) must support the latest radio and optical interfaces. At

advanced nodes, such analog IP blocks are challenging and time-consuming

to design. Faced with competitive pressures around time to market and cost,

many SoC designers are turning to analog IP providers with off-the-shelf

solutions. There are plenty of analog IP providers on the market—according

to Semico, demand for analog IP cores such as analog-to-digital converters

(ADCs) and digital-to-analog converters (DACs) is expected to increase at more

than 17% through 2015

. With readily available analog IP, designers now have

the option to integrate such IP and thus minimize potential challenges that

can occur with doing analog design from scratch—such as synchronization,

noise, and, layout. However, not all analog IP is the same. Choosing the right

solutions can mitigate risks, speed up the design cycle, and guarantee design

performance goals.

How to choose the right building blocks? The life of a designer is always about

trade-offs. From signal sampling rates to power consumption, there are a

variety of criteria to consider when choosing the optimal analog IP for an

SoC—in other words, IP that will support stringent performance, power, and

other requirements. This paper examines six key selection criteria:

• Sampling rate

• Bit resolution

• Architecture

• Process node

• Power consumption

• Die size

6 Key Considerations for Choosing the Right

Analog IP

By Bob Salem and Kevin Yee, Product Directors, Cadence Design Systems

Analog circuitry continues to play a critical role in today’s advanced systems on a chip (SoCs), especially given the rise

of mobile computing and the Internet of Things. Designing with analog designs comes with unique challenges (To

learn more, read our paper, 5 Key Challenges in designing with High-Speed Analog IP Design). One way to address

these challenges and meet time-to-market expectations is by integrating off-the-shelf analog intellectual property

(IP) blocks into the SoC design. This paper discusses six key considerations for choosing the right analog IP for next-

generation mixed-signal designs.

Contents

Introduction .................................1

Sampling Rate: How Much

Speed is Necessary? ..................... 2

Resolution: a Look at Quality

of Signal Sampling .......................2

Architecture .................................2

Process Node: Advantages

and Challenges at 28nm ..............3

Power Consumption and Die Size:

What’s Important in Analog .........3

More than 250 Silicon-Tested

Analog IP Blocks ..........................4

Footnotes ....................................5

For Further Information ................5

Sampling Rate: How Much Speed is Necessary?

Signal speed is an obviously important criterion for data converters. For greater accuracy in rendering analog

signals, the data converter should support fast speeds in the sampling of incoming data. Following the guidance of

the Nyquist sampling theorem, the sampling rate should be higher than twice the highest frequency of the signal,

in order to generate an accurate reproduction of an analog signal in digital form. When evaluating analog IP, the

fastest signal that is targeted for sampling will determine how fast the sample rate must be. Under conventional

thinking, it would appear that faster is better. However, as we noted earlier, life is about trade-offs. So, more speed

also means higher power. The art is to strike a balance between just fast enough and just low enough power.

Data converters that support emerging high-speed communications protocols, such as WiGig (802.11ad), Long

Term Evolution (LTE), and LTE Advanced, require fast sampling rates. WiGig, for instance, runs on a 60GHz

spectrum, with a potential data throughput up to 7Gbps, or 2.16GHz bandwidth (a rate 10X higher than in

801.11n). As a result, the ADC needs to be 10X faster. Such capabilities would bring functions like wireless trans-

mission of uncompressed video to reality.

Resolution: a Look at Quality of Signal Sampling

How fast do you need to sample (as discussed above) and how many bits you select will determine how accurately

you represent your analog signal. This is resolution. The higher your resolution, the more accurate you will be

to represent your original analog signal. In other words, the combination of your sample rate and bit width will

determine the quality of the signal. When designing an SoC for an audio application, strive for as large a number

of sample rates (bits) as possible, to allow higher sensitivity to noise. For typical sensor applications, a sample rate

of six to seven bits can be sufﬁcient.

Effective number of bits (ENOB) provides a holistic measurement of analog-to-digital (A to D) performance. This

metric assesses what the quality of the A to D conversion will be like in a real application, accounting for factors

including noise, temperature, and signals. An ideal ENOB is one that is as high as the number of bits in the ADC.

Architecture

There are a variety of ADC architecture types, each with varying sample rates, resolution, and power efﬁciency.

The successive approximation register (SAR) architecture is the most popular ADC architecture today, as it is very

fast and, with the reuse of each slice of ADC, it is also quite scalable. A single SAR data converter can have sample

rates from 100KSPS to 500MSPS (along with high power efﬁciency and medium-level resolution at 6 to 12 bits).

A parallel SAR converter (as shown in Figure 1) can boast sample rates from 500MSPS to 40GSPS, though with a

medium-level power efﬁciency and resolution (6 to 12 bits). By comparison, the Flash ADC architecture provides

the highest sample rates—100MSPS to 40GSPS—but it also comes with the lowest power efﬁciency and resolution

(three to six bits). Another popular ADC architecture, the sigma delta architecture, features high resolution (10 to

24 bits) but low sampling rate, at 10 SPS to 50 MSPS.

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6 Key Considerations for Choosing the Right Analog IP