Overview
With more microelectromechanical
systems (MEMS) being widely
used for automotive and consumer
electronics, the need for a robust
MEMS and mixed-signal co-design
flow is becoming crucial. This flow
should equally enable system-on-
chip (SoC) and system-in-package
(SiP) approaches. A clear-cut interface
between a MEMS design sub-flow
and the conventional mixed-signal
sub-flow is necessary.
Provided as Virtual Integrated
Computer-Aided Design (VCAD)
Productivity Package, the Cadence®
SIMPLI Mixed-Signal/MEMS Co-design
Methodology handles the special
requirements for a MEMS method-
ology for both SoC and SiP applica-
tions.
SIMPLI ensures efficient handling of
concurrent design/optimization of the
MEMS and electronics while handling
engineering change orders (ECO)
between the two domains.
The Cadence
®
SIMPLI Mixed-Signal/MEMS Co-design Methodology handles the special
requirements for a MEMS methodology for both system-on-chip (SoC) and system-in-package
(SiP) applications. Silicon MEMS Platform Interchange – SIMPLI, which supports Cadence Virtuoso
®
users, ensures efficient handling of concurrent design/optimization of the MEMS and electronics
while handling engineering change orders (ECO) between the two domains.
Cadence SIMPLI Mixed-Signal/MEMS Co-design
Methodology
For Cadence Virtuoso Users
MEMS
Inter-digitized
Sendor
Clock
Tree
C-to-V
Signal
Proc
ADC
MEMS IP Analog + Mixed Signal +
Digital Components
Single Monolithic
CMOS-MEMS
MEMS Design Sub-Flow
Electro-
mechanical
Simulation
Physical
Design
SIMPLI
Functional
Validation
Physical
Integration
Mixed-Signal/MEMS Design
Sub-Flow
Electrical
Simulation
Physical
Design
Foundry Design Kit
IC System Specifications
Electro-Mechanical MEMS Specifications Digital
Analog
(Mixed-Signal)
Top-Down Top-Down
Bottom-Up
Integration
Publishing
Figure 1
www.cadence.com
2
Cadence SIMPLI Mixed-Signal/MEMS Co-design Methodology
A Monolithic Mixed-
signal / MEMS Co-design
Methodology
The MEMS sub-flow follows a
top-down approach starting
with behavioral modeling down
to finite-element simulation.
For the MEMS sub-flow, a
Cadence-based design sub-flow
is readily available, yet the flow
is equally portable to many
third-party MEMS point tools
through the use of SIMPLI.
The proposed MEMS sub-flow
is demonstrated by 18 design
tasks. An x-axis MEMS acceler-
ometer design has been chosen
to demonstrate these design
tasks from specifications to
publishing.
A meet-in-the middle
approach is used for the
mixed-signal sub-flow, a
variant of the Cadence AMS
Design Methodology. This will
decrease the entry barrier for
the integration of the MEMS
structure. On the other hand,
most of the specific steps that
have to be handled by mixed-
signal designers due to the
presence of the MEMS structure
are handled from a single
cockpit called SIMPLI. Thus,
mixed-signal designers will not
need special training on the
MEMS sub-flow.
2A
MEMS
Executable
Specifications
Creation
3A
MEMS
Topology
Selection
2B
MEMS Design
Validation
Strategy
2C
Auxiliary DRC
Rules Creation
5B
MEMS Block
Early Design
Rule Checking
3B
P-Cells
Creation
4B
MEMS Layout
Nominal Design
Generation
4A
Geometrical/
Mechanical
Nominal
Design
6
Geometrical/
Mechanical
Models
Enhancement
7B
Geometrical/
Mechanical
Design
Optimization
7A
Nominal/
Statistical
Verification with
Enhanced
Models
7C
MEMS Layout/
Abstract Final
Design
Generation
8A
Finite-Element
Signoff
8B
N-DOF
Reduced-Order
Model
Generation
8C
MEMS Block
Final Design
Rule Checking
9
MEMS IP
Packaging
8D
MEMS Block
Electrical
Parasitic
Extraction
5A
Nominal Finite
Element
Verification
MEMS Top-Down Functional DesignMEMS
Design
Data
Input
MEMS Top-Down Physical Design
1A
MEMS
Design
Specs
1B
Foundry
Design
Kit
180nm
Figure 2: MEMS Design Sub Flow
2
IC Design
Validation
Strategy
3
AMS Design
Partitioning
4
Block
Specifications
6A
IC Design
Functional
Concept
Validation
7
IC Design
Respecification
9
IC Design
Functional
Performance
Validation
13
IC Post-Layout
Validation
16
IC Design
Functional
Signoff
IC Top-Down Functional Design
IC Top-Down Functional Design
IC Top-Down Functional Design
IC Design
Data Input
1A
Design
Specs
1B
Modified
Foundry
Design Kit
(180nm)
1C
System-Level
Models
1D
System-Level
Testbenches
1E
MEMS
Packaged IP
1F
MEMS DFII
Testbenches
1G
3rd Party IP
1H
Legacy IP
5A
Analog Block
Circuit Design
5E
MEMS IP
Import
5B
Analog Block
Behavioral
Design
8A
Analog Block
Circuit
Optimization
10A
Analog Block
Physical
Estimation
12A
Analog Block
Physical Design
10B
Digital Block
Physical
Estimation
12B
Digital Block
Physical Design
14
Block Physical
Integration
Preparation
5D
Digital
Hierarchical
RTL Design
5C
Legacy and 3rd
Party IP Import
8B
Digital Block
Synthesis
6B
IC Design
Early
Floorplanning
11
IC Refinement
Floorplanning
15
IC Design
Assembly
Figure 3: Mixed Signal / MEMS Design Sub Flow