Product Qualification Report –JFETs
January 2019 United Silicon Carbide, Inc. 2
www.unitedsic.com
Scope
This report summarizes the AEC-Q101 qualification results for the UJ3N family of
discrete SiC JFETs in TO-247-3L plastic packages.
The environmental stress tests listed below are performed with pre-stress and post-
stress electrical tests. Reviewing the electrical results for new failures and any
significant shift performance satisfies the AEC-Q101 qualification requirements, as well
as UnitedSiC Quality requirements.
Reliability Stress Test Summary
Test Name Test Standard
# Samples
x # Lots
Failures
High Temperature
Gate Reverse Bias
(HTGRB)
MIL-STD-750-1
M1038 Method A
(1000 Hours)
T
J
=175
o
C, V
GS
=20V, V
DS
=80% V
max
77x4 lots 0/308
Highly Accelerated
Stress Test
(HAST)
JESD22 A-110
(96 Hours)
T
A
=130
o
C/85%RH, V
GS
=0V, V
DS
=42V
77x4 lots 0/308
Intermittent Operating
Life
(IOL)
MIL-STD-750
Method 1037
DT
J
≥125ºC, 3000 cycles
(5 minutes on/ 5 minutes off)
77x4 lots 0/308
Temperature Cycle
(TC)
JESD22 A-104
(1000 Cycles)
77x4 lots 0/308
Autoclave
(PCT)
JESD22 A-102
121°C/ RH = 100%, 96 hours, 15psig
77x4 lots 0/308
Parametric Verification Per Datasheet
100% FT x 4
lots
Physical Dimensions Per AEC-Q101 Rev D
30x1
packages
0/30
Bondline Thickness Per Assembly Spec 10x4 lots 0/40
Die Shear Per Assembly Spec 10x4 lots 0/40