Engineer-to-Enginee r Not e EE-402

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Synchronous System Halt and Run on the ADSP-CM41x Proc essor

Contributed by Manjunath, Manasa, Kiranmai Pernapati and Prasanth Rajagopal Rev 1 – March 21, 2019

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Introduction

The ADSP-CM41xF is a dual core mixed-signal control processor containing an Arm

Cortex

-M4

processor core and an Arm Cortex-M0 processor core. It includes several peripherals, such as the pulse-

width modulators (PWM), that support motor control and inverter applications. Development on the

processor is supported through the IAR Embedded Workbench and Keil™ MDK-Lite tool chains. The

synchronous halt operation is used when:

 The peripherals must stop running due to the debugger entering emulation mode (halt execution)

 The peripherals must star t running due to the debugger exiting f rom emulation mode (resume execution)

 External components (such as motors) that are connected and PWMs must synchronously halt or run

due to the execution or halt of the control code logic.

Synchronous halt operation is not supported as received by debuggers like IAR and Keil. However, the

ADSP-CM41xF processor is designed to support the operation in hardware. The processor uses the

Embedded Cross Trigger (ECT) which consists of the Cross Trig ger Inte rface (C T I) and the C ros s T ri gger

Matrix (CTM). Both the IAR Embedded Workbench C-SPY debugger and Keil debugger interface and

drive the J-L ink Lite e mulator that supports the ADSP-CM41xF processor family. The C-SPY and µVision

support macros that can be executed when specific events occur.

This application note provides an IAR EWARM and Keil debug scripts to set up the CTI registers to

synchronously halt and run various peripherals in the system. The zip file

[1]

associated with this note

includes some examples that can be executed on an ADSP-CM41xF processor evaluation board.

Synchronous System Halt and Run on the ADSP-CM41x Processor (EE-402) Page 2 of 17

Figure 1 and Figure 2 provide examples of synchronous halt and run in a system.

Figure 1. Synchronous Halt and Run – PWM

Figure 2. Synchronous Halt and Run – GPIO

Embedded Cross Trigger (ECT)

ECT provides an interface to the CoreSight debug system enabling the subsy stems to intera ct (cross trigger)

with each other. The ma in function of the ECT (C TI and CTM) is to pass de bug events from one conne cted

subsystem to another. Program execution on both of the subs ystems can be stopped at the same ti me. The

different subsystems connected to the ECT depend on the processor design. For example, in a

multiprocessor system, the interface can connect to each of the cores and to the trace subsystem. For a

uniprocessor system, the interface can connect to the core and trace subsystem.

 CTI – A CoreSight component for enabling the cross triggering of events across a system

 CTM – A CoreSight component for connecting multiple cross trigger interfaces

Figure 3 shows the debug trigger flow sequence. On each CTI, there are four channels, eight inputs, and

eight output debug triggers. All of the eight inputs and outputs can be mapped to a single channel or different

channels based on the debug trigger-to-channel mapping. When a trigger input occurs, it creates a channel