DRAFT
STEVAL-MKI109V2 Schematic diagrams
Figure 1. Circuit schematic (1 of 2)
INT2
INT1
18pF
Cosc2
18pF
Cosc1
1M
R7
OSCIN OSCO UT1
2
3
4
16MHz
Os c1
D2 D3
100R
R24
100R
R25
ST
PD
1
2
3
ST
JP4
1
2
3
PD
JP5
PD_u
ST_u
1
2
3
HP
JP6
HP
HP _u
VDD
VDD
VDD
10K
R11
10K
R12
10K
R19
RledGled
100R
R23
100R
R22
VDD
SW1
VDD
10K
R17
SW1
SW2
VDD
10K
R18
SW2
BOOT0
10K
R14
BOOT1
10K
R13
VDD
10K
R6
10K
R5
10K
R4
10K
R3
10K
R2
Not Mo unted
JTMS_SWDIO
JTDI
JNTRST
JTDO
JTCK_SWCLK
NRST
1
2
3
4
5
6
7
8
9
10
11
12
Header 12
J4
24
23
22
21
20
19
18
17
16
15
14
13
Header 12
J5
PD
ST
HP
OUT2
OUT1
OUT4
OUT5
INT2
INT1
SCL_DEV
SDA_ DEV
SDO_DEV
CS_DEV
Vref
O1
O2
OUT3
OUT6
O3
DIL24 Device Adapter
D4 D5
1
3
5
7
9 10
8
6
4
2
SWD Connector
J1
VDD
1
2
JP7
VDD
VD D VDD
VDD
100nFC5
100nF
C8
10nF
C17
+
1uF
C12
+
4.7uF
C10
VDD
VDD
VDD
VDD
VD D
100nFC4
Vref_u
OUT4 _u
OUT5 _u
OUT2 _u
OUT1 _u
INT2
INT1
JTMS_SWDIO
OSCIN
OSCO UT
I2C_SCL
I2C_SDA
4.7K
R26
4.7K
R27
VD D
NRST
BOOT0
USBD P
USART RX
USART TX
JTDI
JNTRST
JTDO
JTCK_SWCLK
USBD M
Rled
Gl ed
SW1
SW2
BOOT1
SW3
100nF
C7
OUT3 _u
OUT6 _u
I2C_SCL
I2C_SDA
0RR16
0RR15
SCL_DEV
SDA_ DEV
100nF
C26
VDD
CS_DEV
PD_u
ST_u
SPI2_SCL
SPI2_SD A
PA3/ADC3
17
Vs s 4
18
Vdd4
19
PA4/NSS/ADC4
20
PA5/SCK/ADC5
21
PA6/MISO/ADC6
22
PA7/MOSI/ADC7
23
PC4/ADC14
24
PC5/ADC15
25
PB0/ADC8
26
PB1/ADC9
27
PB2/BO OT1
28
PB10
29
PB11
30
Vs s 1
31
Vdd1
32
PB12/SPI2_NSS
33
PB13/SPI2_SCK
34
PB14/SPI2_MISO
35
PB15/SPI2/MOSI
36
PC6
37
PC7
38
PC8
39
PC9
40
PA8/MCO
41
PA9/USART1_TX
42
PA10/ USART1_RX
43
PA11/USBDM
44
PA12/ USBDP
45
PA13/JTMS-SWDIO
46
Vs s2
47
Vdd2
48
PA14/JTCK/
SWCLK
49
PA15/JTDI
50
PC10
51
PC11
52
PC12
53
PD2
54
PB3/JTDO
55
PB4/JNTRST
56
PB5
57
PB6/I2C_SCL
58
PB7/I2C_SDA
59
BOOT0
60
PB8
61
PB9
62
Vss3
63
Vdd 3
64
Vbat
1
PC13/Tamper/RTC
2
PC14/OSC32in
3
PC15/OSC32out
4
PD0/OSCin
5
PD1/OSCout
6
NRST
7
PC0/ADC10
8
PC1/ADC11
9
PC2/ADC12
10
PC3 /ADC1 3
11
Vs sA
12
VddA
13
PA0/WKUP/ADC0
14
PA1 /ADC1
15
PA2 /ADC2
16
STM32F103RET6
Copper area overlapped
0RR32
0RR33
SPI2_SDA
SPI2_SCL
SDO_D EV
Vdd_ dut
1
2
3
4
5
6
7
8
9
10
11
12
Header 12X 2
JP2
1
2
3
4
5
6
7
8
9
10
11
12
Header 12X 2
JP3
GP_ GPIO1
GP_ GPIO1
USB_ Disc
Not Mo unted
7
In-
6
In+
5
- +
TS924
U1B
14
In-
13
In+
12
- +
TS924
U1D
7
In-
6
In+
5
- +
TS924
U3B
14
In-
13
In+
12
- +
TS924
U3D
VDD
VDD
VDD
VDD
OUT1
OUT2
OUT3
OUT4
OUT3_u
OUT4 _ u
u_1TUO
u_2TUO
1
In-
2
In+
3
- +
TS924
U1A
8
In-
9
In+
10
- +
TS924
U1C
1
In-
2
In+
3
- +
TS924
U3A
8
In-
9
In+
10
- +
TS924
U3C
VDD
VDD
VDD
VDD
OUT5
OUT6
u_5TUO
u_6TUO
Vref_u
Vref
GP_ le d
VD D
100R
R30
D6
GP_ led
1
In-
2
In+
3
-+
TS922
U4A
7
In-
6
In+
5
-+
TS922
U4B
VD D
VD D
O2
HP _u
O2_ u
O1_ u
O3_u
O1
O3
O1_u
O3_u
R0
R10
R0
R21
R0
R29
R0
R9
R0
R20
R0
R28
Not Mo unted
USBD M
USBD P
USB_ Disc
USBD M
USBD P
USB_ Disc
O2_u
1
2
JP10
1
2
JP9
Not Mo unted
Not Mo unted
Not Mo unted
1
2 3
Header 3
JP11
1
2
3
Header 3
JP8
Vdd_ dut
Vdd_ dut
VD D
CE_RF
CS_RF
SCK_RF
MOSI_RF
MISO _RF
IRQ_RF
SCK_RF
MISO_RF
MOSI_RF
CE_RF
CS_RF
IRQ_RF
1
2
3
4
5
6
7
8
MHDR1X8
JP12
AM07277v1
DRAFT
Figure 2. Circuit schematic (2 of 2)
53"? 6
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22
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1
K
2
6$ $
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2
K
2
53"? 6
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1
K
2
6$ $
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53"? $I SC
2
2
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6B US
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53",#0
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6OUT
LD S XX 5
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U&
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0OWER3UPPLY
*
40
53"?6
#URRENT?-EASURE
*0
6D D?D UT
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6$ $
4!.4
6PS
53"$ -
53"$ 0
53"? $I SC
53"$ -
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53"? $I SC
6D D?D UT
6D D?D UT
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