eGaN® FET DATASHEET
EPC2001C
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1
EPC2001C eGaN® FETs are supplied only in
passivated die form with solder bars
Applications
• High-Frequency DC-DC Conversion
• Industrial Automation
• Synchronous Rectication
• Class-D Audio
• Low Inductance Motor Drives
Benets
• Ultra High Eciency
• Ultra Low Switching and Conduction Losses
• Zero Q
RR
• Ultra Small Footprint
EFFICIENT POWER CONVERSION
HAL
EPC2001C – Enhancement Mode Power Transistor
V
DS
, 100 V
R
DS(on)
, 7 mΩ
I
D
, 36 A
G
D
S
Maximum Ratings
PARAMETER VALUE UNIT
V
DS
Drain-to-Source Voltage (Continuous) 100
V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 120
I
D
Continuous (T
A
= 25˚C, R
θJA
= 7.3) 36
A
Pulsed (25°C, T
PULSE
= 300 µs) 150
V
GS
Gate-to-Source Voltage 6
V
Gate-to-Source Voltage -4
T
J
Operating Temperature -40 to 150
°C
T
STG
Storage Temperature -40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
R
θJC
Thermal Resistance, Junction to Case
1
°C/W R
θJB
Thermal Resistance, Junction to Board
2
R
θJA
Thermal Resistance, Junction to Ambient (Note 1)
54
Note 1: R
θJA
is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
All measurements were done with substrate connected to source.
Static Characteristics (T
J
= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BV
DSS
Drain-to-Source Voltage V
GS
= 0 V, I
D
= 300 μA 100 V
I
DSS
Drain-Source Leakage V
GS
= 0 V, V
DS
= 80 V 100 250 µA
I
GSS
Gate-to-Source Forward Leakage V
GS
= 5 V 1 5
mA
Gate-to-Source Reverse Leakage V
GS
= -4 V 0.1 0.25
V
GS(TH)
Gate Threshold Voltage V
DS
= V
GS
, I
D
= 5 mA 0.8 1.4 2.5 V
R
DS(on)
Drain-Source On Resistance V
GS
= 5 V, I
D
= 25 A 5.6 7 mΩ
V
SD
Source-Drain Forward Voltage I
S
= 0.5 A, V
GS
= 0 V 1.7 V
www.epc-co.com/epc/Products/eGaNFETs/EPC2001C.aspx
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment
leveraging the infrastructure that has been developed over the last 60 years. GaN’s exceptionally
high electron mobility and low temperature coecient allows very low R
DS(on)
, while its lateral
device structure and majority carrier diode provide exceptionally low Q
G
and zero Q
RR
. The end
result is a device that can handle tasks where very high switching frequency, and low on-time are
benecial as well as those where on-state losses dominate.
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 2
eGaN® FET DATASHEET
EPC2001C
I
D
– Drain Current (A)
V
DS
– Drain-to-Source Voltage (V)
150
120
90
60
30
0
1 1.5 2 2.5 3
V
GS
GS
GS
GS
= 5 V
V
= 4 V
V
= 3 V
V
= 2 V
I
D
– Drain Current (A)
V
GS
– Gate-to-Source Voltage (V)
150
120
90
60
30
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
R
DS(on)
– Drain to Source Resistance (mΩ)
R
DS(on)
– Drain to Source Resistance (mΩ)
V
GS
– Gate-to-Source Voltage (V)
20
25
15
10
5
0
2.5 2 3 3.5 4 4.5 5
V
GS
– Gate-to-Source Voltage (V)
25
15
20
10
5
0
2.5 2 3 3.5 4 4.5 5
I
D
= 25 A
25˚C
125˚C
Figure 1: Typical Output Characteristics at 25°C
Figure 2: Transfer Characteristics
Figure 3: R
DS(on)
vs. V
GS
for Various Currents Figure 4: R
DS(on)
vs. V
GS
for Various Temperatures
0 0.5
I
D
= 10 A
I
D
= 20 A
I
D
= 40 A
I
D
= 80 A
V
DS
= 3 V
25°C
125°C
Dynamic Characteristics (T
J
= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
C
ISS
Input Capacitance
V
DS
= 50 V, V
GS
= 0 V
770 900
pFC
OSS
Output Capacitance
430 650
C
RSS
Reverse Transfer Capacitance
10 15
R
G
Gate Resistance
0.3 Ω
Q
G
Total Gate Charge
V
DS
= 50 V, V
GS
= 5 V, I
D
= 25 A 7.5 9
nC
Q
GS
Gate-to-Source Charge
V
DS
= 50 V, I
D
= 25 A
2.4
Q
GD
Gate-to-Drain Charge
1.2 2
Q
G(TH)
Gate Charge at Threshold
1.6
Q
OSS
Output Charge
V
DS
= 50 V, V
GS
= 0 V 31 45
Q
RR
Source-Drain Recovery Charge
0
All measurements were done with substrate connected to source.
Note 2: C
OSS(ER)
is a xed capacitance that gives the same stored energy as C
OSS
while V
DS
is rising from 0 to 50% BV
DSS
.
Note 3: C
OSS(TR)
is a xed capacitance that gives the same charging time as C
OSS
while V
DS
is rising from 0 to 50% BV
DSS
.