January 2013 Altera Corporation
AN-662-1.0 Application Note
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Arria V and Cyclone V Design Guidelines
This application note provides a set of checklists that consist of design guidelines,
recommendations, and factors to consider when you create designs using the
Arria
®
V or Cyclone
®
V FPGAs.
■ Use this document to help you plan the FPGA and system early in the design
process, which is crucial for a successful design.
■ Follow Altera’s recommendations throughout the design process to achieve good
results, avoid common issues, and improve your design productivity.
Figure 1 shows the Arria V and Cyclone V design flow. The sections in this document
provide the checklists and guidelines for each part of the design flow.
1 For the Arria V and Cyclone V SoC FPGA device variants, the guidelines in this
document are applicable only to the FPGA portion of the devices.
Figure 1. Arria V and Cyclone V Design Flow
Specifications
Early Planning Design Entry
Design Specifications
• IP Selection
Device Selection
Early Board Design
Planning
Early Pin Planning
and I/O Assignment
Hierarchical Team-based
Design Planning
Design Implementation
Synthesis
and Compilation
Timing Optimization
and Analysis
Functional Timing
Simulation
Formal Verification
Power Analysis
and Optimization
I/O and Clock Planning
I/O Features and
Pin Connections
Clock Planning
I/O SSN Considerations
Board Design
Power Pins Planning
Configuration Pins
Planning
Page 2 Before You Begin
Arria V and Cyclone V Design Guidelines January 2013 Altera Corporation
Before You Begin
Before you begin planning and designing your FPGA system, familiarize yourself
with the FPGA device features, and the design tools and IP that are available for the
Arria V or Cyclone V device family.
Table 1. Prerequisites Checklist (Part 1 of 2)
No. v Checklist items
1.
Read through the Device Overview of the FPGA
The Device Overview provides an overview of the capabilities and options available for a
device family. Read through the document to familiarize yourself with the device family
offerings and general features.
For an overview of each FPGA device family, refer to the following documents:
■ Arria V Device Overview
■ Cyclone V Device Overview
2.
Estimate design requirements
Create a rough estimate of the design in the following terms:
■ Basic functions of the product
■ Similar previous designs
■ General device requirements
3.
Review available design tools
Consider the available design, estimators, system builders, and verification tools. The
following items are some of the available tools provided by Altera:
■ The Quartus
®
II software for design, synthesis, simulation, and programming;
including integration with Qsys, simulation tools, and verification tools.
■ The Qsys system integration tool—next generation SOPC Builder that automatically
generates interconnect logic to connect intellectual property (IP) functions and
subsystems.
■ The Mentor Graphics
®
ModelSim
®
-Altera
®
simulation software.
■ The TimeQuest Timing Analyzer for static timing analysis with support for Synopsys
®
Design Constraints (SDC) format.
■ The PowerPlay Power Analyzer for power analysis and optimization.
■ The SignalProbe and SignalTap II Logic Analyzer debugging tools.
■ The External Memory Interface Toolkit available in the Quartus II software.
■ The Transceiver Toolkit for real-time validation of transceiver link signal integrity.
For more information, visit the following pages on the Altera website:
■ Design Tools & Services
■ Design Software Support
■ Transceiver Toolkit
For a guideline to migrate from SOPC Builder to Qsys, refer to AN 632: SOPC Builder to
Qsys Migration Guidelines.