September 2015 Altera Corporation

ES-01036-2.8 Errata Sheet

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Errata Sheet for Arria V Devices

This errata sheet provides information about known device issues affecting Arria

production devices.

Device Errata for Arria V Production Devices

Table 1 lists the specific device issues and the affected Arria V production devices.

Table 1. Arria V Production Device Issues (Part 1 of 2)

Issue Affected Devices Planned Fix

“JTAG Programming of 28-nm Devices” All Arria V Devices None

“EMAC RMII PHY Interface is Only Supported Through the

FPGA Fabric”

All Arria V SX and ST Devices None

“Hard Processor System Level 2 Cache Error Correction

Code”

Enabling ECC in the L2 cache may cause false ECC interrupts.

All Arria V SX and ST Devices Rev C silicon

“EMIF Maximum Frequency Specification Update”

The EMIF maximum frequency specification has been

updated.

All Arria V GX and GT Devices None

“SEU Internal Scrubbing”

SEU internal scrubbing has usage restrictions.

All Arria V GX and GT Devices None

“Fractional PLL Phase Alignment Error”

The fractional PLL (fPLL) has a silicon sensitivity that causes

the static phase error to operate beyond the Quartus

software expectation.

All Arria V GX and GT Devices Refer to Table 4.

“Bit Errors on the LVDS RX Channels Using DPA”

DPA or soft-CDR mode is not supported for specific LVDS

data rates.

All Arria V GX and GT devices

For the Quartus

II and die

revision solutions in

different LVDS DPA data

rate ranges, refer to Table 5

and Table 6.

Devices that support the

complete range of LVDS

DPA data rate will begin

rolling out in Q3 2013.

“Configuration via Protocol (CvP)”

CvP and Autonomous HIP functionality is not supported.

All Arria V Devices except

5AGTC7, 5AGXA7, 5AGXA5,

5ASXB3, 5ASXB5, 5ASTD3

and 5ASTD5 devices.

Devices that are CvP

capable will begin rolling

out in Q2 2013

“Usermode High Icc”

High Icc observed when entering User mode.

All Arria V GX and GT Devices None

Page 2 Device Errata for Arria V Production Devices

September 2015 Altera Corporation

Errata Sheet for Arria V Devices

JTAG Programming of 28-nm Devices

JTAG configuration of 28-nm devices does not operate correctly when you initiate a

PAUSE_DR

instruction during configuration. In this scenario, JTAG configuration fails

when pausing configuration in the middle of the bit stream by entering into the

PAUSE-DR state and continuing to clock the TCK input. The failure is indicated by

CONF_DONE

staying low after all of the data has been clocked into the FPGA while

nSTATUS

remains high.

The PAUSE-DR feature works correctly with normal IEEE 1149.1 JTAG test

operations.

Workaround

If you require pausing in the middle of the bit stream during JTAG configuration, halt

the TCK and do not enter the PAUSE-DR state. Restart the TCK when you resume the

configuration.

EMAC RMII PHY Interface is Only Supported Through the FPGA Fabric

The default setting of the

physel_x

field in the System Manager EMAC Control

Group's

ctrl

Because the HPS I/O timings do not support RMII protocol, encodings

0x0

and

0x1

are the only valid values in the

physel_x

field. Selecting the

0x0

encoding routes the

GMII/MII signals to the FPGA fabric only, and selecting the

0x1

encoding routes the

RGMII interface to the HPS I/O only. If the

physel_x

encoding is left as

0x2

, the HPS

PHY interface does not function properly.

Workaround

If an RMII PHY interface is required, the

physel_x

field should be set to

0x0

so that the

GMII/MII signals are routed to the FPGA. You can design an RMII soft adaptor in the

FPGA configuration file that converts these MII signals to an RMII PHY interface that

is mapped to the FPGA I/O pins. Refer to the “Programming Model” section of the

EMAC chapter in the Arria V Device Handbook, Volume 3: Hard Processor System

Technical Reference Manual for more information about how to initialize the EMAC

Controller and interface.

“Unused or Idle Transmitter Maximum Data Rate

Degradation”

Currently unused or idle transmitter's maximum data rate can

degrade over a period.

All Arria V GX and GT Devices None

“False Configuration Failure in Active Serial Multi-Device

Configurations”

In Active Serial (AS) multi-device configuration mode, the

error checking for CONF_DONE release may not operate

correctly.

All Arria V devices None

“Hard Processor System PLL Lock Issue After Power-on

Reset or Cold Reset”

All Arria V SX and ST Devices Rev D silicon: March, 2015

Table 1. Arria V Production Device Issues (Part 2 of 2)

Issue Affected Devices Planned Fix