March 2012 Altera Corporation

ES-01026-7.6 Errata Sheet

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Errata Sheet for Stratix III Devices

This errata sheet provides updated information on known device issues affecting

Stratix

III devices.

Production Device Issues for Stratix III Devices

Ta bl e 1 lists the specific issues and which Stratix III devices are affected by each issue.

Table 1. Issues for Stratix III Devices (Part 1 of 3)

Issue Affected Devices Planned Fix

“PLL phasedone Signal Stuck at Low”

In some cases, the Stratix III phase-locked loop (PLL) blocks

exhibit the phasedone signal stuck at low during the PLL dynamic

phase shift.

All Stratix III devices

Quartus

II software version

12.0 and later.

“Error Detection CRC Feature, When Enabled, May Cause the

MLAB RAM Blocks to Operate Incorrectly” on page 3

Error Detection CRC feature, when enabled, may cause the MLAB

RAM blocks to operate incorrectly.

All Stratix III Devices

EP3SL50 Revision G

EP3SL70 Revision F

EP3SL110 Revision I

EP3SL150 Revision H

EP3SL200 Revision G

EP3SL340 Revision E

EP3SE50 Revision D

EP3SE80 Revision G

EP3SE110 Revision F

EP3SE260 Revision F

“Remote System Upgrade Feature” on page 4

Remote System Upgrade feature fails when loading an invalid

application configuration image.

All Stratix III Devices —

“CRC Error Injection Feature” on page 4

The CRC error injection feature may not operate correctly.

All Stratix III Devices —

MLAB final timing models were updated post Quartus II Software

version 8.1. Only a subset of designs using MLAB blocks are

affected. See the information in the second paragraph of

“Updated MLAB Final Timing Model (Affecting a Subset of MLAB

Designs)” on page 5.

EP3SL110

EP3SL150

EP3SL340

EP3SE110

EP3SE80

—

“Updated LVDS Final Timing Model” on page 5

LVDS final timing models were updated post Quartus II Software

version 8.1.

All Stratix III Devices —

Page 2 Production Device Issues for Stratix III Devices

Errata Sheet for Stratix III Devices March 2012 Altera Corporation

Dynamic phase alignment (DPA) circuitry in Stratix III devices

might get stuck at the initial configured phase or move to the

optimum phase after a longer than expected period of time.

All Stratix III Devices —

CCPT

Power-Up Issue. Device may fail to power-up successfully. All Stratix III Devices —

CRC_ERROR

may toggle unexpectedly in user mode without

detecting an actual SEU.

All Stratix III Devices —

M9K and M144K RAM blocks can be put into a locked, inactive

state when driven by a clock with a very narrow pulse (for

example, a glitch).

All Stratix III Devices —

Stratix III devices can fail JTAG configuration in certain positions

of the JTAG chain, depending on the setup conditions.

3SL150 Revision B

and earlier

3SE50/L70/E110/

E260/L340 Revision A

3SL150 Revision C

3SE50/L70/E110/E260/L340

Revision B

EP3SL200

EP3SL110

EP3SL50

EP3SE80

Interface timing issues with the LVDS hard macro.

All Stratix III devices All Stratix III devices

The dynamic phase alignment (DPA) lock signal

(

rx_dpa_locked) does not assert on some channels during link

initialization.

All Stratix III devices All Stratix III devices

The DPA circuit in the EP3SL150 ES devices fails to lock and data

is corrupted at data rates of 150 Mbps to 385 Mbps and data

rates above 622 Mbps.

EP3SL150 ES devices EP3SL150 production devices

Analog-to-digital converter (ADC) for temperature sensing diode

(TSD) no longer supported.

All Stratix III ES and

production devices

—

TSD must have V

CCPT

powered on to operate.

Revision A of

EP3SE50, EP3SL70,

EP3SE110, EP3SE260,

EP3SL340

Revisions A and B of

EP3SL150 devices

Future revisions of the affected

Stratix III devices

Device may enter power-on reset (POR) during reconfiguration

cycle. New information for “Device Reconfiguration Issue” on

page 9.

Revision A of

EP3SE50, EP3SL70,

EP3SE110, EP3SE260,

EP3SL340

Revisions A and B of

EP3SL150 devices

Future revisions of the affected

Stratix III devices

Write speed decrease for M144K blocks in certain modes.

Revision A of

EP3SE50, EP3SL70,

EP3SE110, EP3SE260,

EP3SL340

Revisions A and B of

EP3SL150 devices

Future revisions of the affected

Stratix III devices

MLAB RAM block size changed from 64x10 or 32x20 (640 bits)

to 16x20 (320 bits).

All Stratix III ES and

production devices

—

The TSD is not backwards compatible with Stratix II devices.

EP3SL150 ES devices EP3SL150 production devices

Table 1. Issues for Stratix III Devices (Part 2 of 3)

Issue Affected Devices Planned Fix