Arria V Avalon-ST Interface for PCIe
Solutions
User Guide
Last updated for Quartus Prime Design Suite: 15.1
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UG-01105_avst
2017.05.12
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Contents
Datasheet ............................................................................................................ 1-1
Arria V Avalon-ST Interface for PCIe Datasheet ................................................................................... 1-1
Features .........................................................................................................................................................1-2
Release Information ....................................................................................................................................1-6
Device Family Support ............................................................................................................................... 1-6
Congurations .............................................................................................................................................1-7
Example Designs.......................................................................................................................................... 1-9
Debug Features ..........................................................................................................................................1-11
IP Core Verication .................................................................................................................................. 1-11
Compatibility Testing Environment ........................................................................................... 1-11
Performance and Resource Utilization .................................................................................................. 1-11
Recommended Speed Grades ..................................................................................................................1-11
Creating a Design for PCI Express.......................................................................................................... 1-12
Getting Started with the Arria V Hard IP for PCI Express ............................... 2-1
Qsys Design Flow.........................................................................................................................................2-2
Generating the Testbench .............................................................................................................. 2-3
Simulating the Example Design .................................................................................................... 2-3
Generating Synthesis Files.............................................................................................................. 2-4
Understanding the Files Generated............................................................................................... 2-4
Understanding Physical Placement of the PCIe IP Core ........................................................... 2-5
Compiling the Design in the Quartus Prime Soware............................................................... 2-5
Modifying the Example Design .................................................................................................................2-8
Using the IP Catalog To Generate Your Arria V Hard IP for PCI Express as a Separate
Component..............................................................................................................................................2-8
Parameter Settings...............................................................................................3-1
Avalon-ST System Settings ........................................................................................................................ 3-1
Link Capabilities ......................................................................................................................................... 3-4
Port Function Parameters Shared Across All Port Functions................................................................ 3-5
Device Capabilities ..........................................................................................................................3-5
Error Reporting ............................................................................................................................... 3-7
Link Capabilities ..............................................................................................................................3-8
Slot Capabilities ...............................................................................................................................3-8
Power Management ...................................................................................................................... 3-10
Port Function Parameters Dened Separately for All Port Functions................................................3-10
Base Address Register (BAR) and Expansion ROM Settings ..................................................3-10
Base and Limit Registers for Root Ports .................................................................................... 3-11
Device Identication Registers for Function <n>..................................................................... 3-12
Func <n> Device ...........................................................................................................................3-13
Func <n> Link................................................................................................................................ 3-13
TOC-2
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