Altera Phase-Locked Loop (Altera PLL) IP Core User
Guide
2017.06.16
UG-01087
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e Altera PLL megafunction IP core allows you to congure the settings of PLL.
Altera PLL IP core supports the following features:
• Supports six dierent clock feedback modes: direct, external feedback, normal, source synchronous,
zero delay buer, and LVDS mode.
• Generates up to 18 clock output signals for the Arria
®
V and Stratix
®
V devices and nine clock output
signals for the Cyclone
®
V device.
• Switches between two reference input clocks.
• Supports both the adjacent PLL (adjpllin) and the C-Counter clock source (cclk) inputs to connect
with an upstream PLL in PLL cascading mode.
• Supports PLL output cascading.
• Generates the Memory Initialization File (.mif) and allows PLL dynamic reconguration.
Related Information
• Introduction to Altera IP Cores
Provides more information about the Altera IP cores and the parameter editor.
• Operation Modes on page 9
• Output Clocks on page 9
• Reference Clock Switchover on page 10
• PLL-to-PLL Cascading on page 10
• PLL Output Counter Cascading on page 14
Device Family Support
e Altera PLL IP core supports the Arria V, Cyclone V, and Stratix V device families.
Altera PLL IP Core Parameters
e Altera PLL IP core parameter editor appears in the PLL category of the IP Catalog.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of
Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specications before relying on any published information
and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
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Altera PLL IP Core Parameters - General Tab
Table 1: Altera PLL IP Core Parameters - General Tab
Parameter Legal Value Description
Device Speed Grade Stratix V: 1–4,
Arria V: 3–6,
Cyclone V: 6–
8
Species the speed grade for a device. e lower the number,
the faster the speed grade.
PLL Mode Integer-N PLL
or Fractional-
N PLL
Species the mode used for the Altera PLL IP core. e
default mode is Integer-N PLL.
Reference Clock Frequency — Species the input frequency for the input clock, refclk, in
MHz. e default value is 100.0 MHz. e minimum and
maximum value is dependent on the selected device. e
PLL reads only the numerals in the rst six decimal places.
2
Altera PLL IP Core Parameters - General Tab
UG-01087
2017.06.16
Altera Corporation
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
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