Engineer-to-Engineer Note EE-393

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Protecting ADSP-CM41x Devices from Input Clock/Power Supply Faults

Contributed by David H. Rev 1 – January 3, 2017

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Introduction

The ADSP-CM41x processors feature peripherals such as the Oscillator Watchdog (OSCWD), Oscillator

Comparator Unit (OCU), and Voltage Monitoring Unit (VMU), which can be used to help determine faults

in the clocks, identify power supply issues for the processor, and allow for a controlled shutdown of the

flash memory and set the general-purpose I/O pins (GPIOs) to safe states. This EE-note describes how to

use these architectural blocks effectively in systems designed around ADSP-CM41x devices.

Oscillator Watchdog (OSCWD)

The Oscillator Watchdog is part of the Clock Generation Unit (CGU) and is used to monitor the system

clock (CLKIN0) for issues such as bad upper and lower frequency limits and harmonic oscillation problems.

OSCWD Operation

The OSCWD uses an internal auxiliary clock with a frequency of 1 MHz, which is used as a reference point

for detection of frequency oscillation and limit issues.

Configuring the OSCWD

The OSCWD has a single control register, OSCWDCTL, located in the CGU register group. This register

provides access to several configurable features:

 Fault Pin Disable

 OSCWDCTL Register Lock

 Watchdog Lower Frequency Limit

 Harmonic Oscillation Detection Enable

 Clock Not Good Enable

 Bad Oscillator Frequency Limit

 Bad Oscillator Frequency Limit Detection Enable

 Fault Enable

 OCU Monitor Disable

Protecting ADSP-CM41x Devices from Input Clock/Power Supply Faults (EE -393) Page 2 of 15

Oscillator Comparator Unit (OCU)

While the OSCWD monitors the CLKIN input to the device, the Oscillator Comparator Unit (OCU)

monitors the frequency of SYSCLK0, which is an output clock from the on-chip PLL on ADSP-CM41x

devices. If a fault, frequency drift, or other clock errors occur in the SYSCLK0 domain, it is possible to

generate both a fault and an interrupt from the OCU. Combined with the OSCWD, this provides the ability

to monitor the entire clock path from the crystal/oscillator input to the clock supplied to the peripherals.

OCU Operation

The OCU monitors the frequency of the input clock using an additional low frequency oscillator (LFO)

input. If the frequency drift of the input clock exceeds specification, a fault is issued. The OCU can also

detect gross frequency errors on either clock. Errors are reported to the System Event Controller (SEC);

and, in the case of a dead input clock, a fault will occur.

The OCU has two operational modes:

 Manual - a single detection cycle is run (stops upon completion whether a fault occurs or not and

no longer monitors clocks).

 Automatic - a continuous detection cycle is run (remains enabled and continues monitoring the

clocks until manually stopped, even if a fault occurred).

In both modes, an interrupt is generated and a fault occurs when a clock issue is detected.

Configuring the OCU

The OCU has several registers that need to be configured before it can be enabled. To configure the OCU,

the Clock Reference Count, the PPM of the clock source, and the PPM of the crystal LFO clock must be

known. To determine the Clock Reference Count, use the following equation:

Clock Reference Count = LFO_Frequency / 16

Since the ADSP-CM419F EZ-Kit® evaluation system

[1]

uses a LFO frequency of 16 MHz, the above

equation yields a Clock Reference Count of 1 MHz. The input and LFO clock sources populated on the EZ-

KIT evaluation system both have a PPM of 50.

Voltage Monitoring Unit (VMU)

The Voltage Monitoring Unit (VMU) provides over-voltage and under-voltage detection by monitoring the

DD_EXT

and V

DD_INT

power domains and generates asynchronous signals if the voltages exceed or drop

below the programmable limits. The VMU also generates a control signal for the power sequencing

requirements of the embedded flash memory, even if the VMU itself is disabled.

The VMU module supports the following safety features:

• Over-voltage and under-voltage detection on V

DD_INT

and V

DD_EXT

• Programmable under-voltage thresholds

• Generates flash memory power-down signal during power event

• Glitch rejection

• Programmable (1  17 s) Fault Delay signal

• GPIO Pin Safe States