PDU17F
Doc #97005 DATA DELAY DEVICES, INC. 1
1/14/97 3 Mt. Prospect Ave. Clifton, NJ 07013
7-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU17F)
FEATURES PACKAGES
• Digitally programmable in 128 delay steps
• Monotonic delay-versus-address variation
• Two separate outputs: inverting & non-inverting
• Precise and stable delays
• Input & outputs fully TTL interfaced & buffered
• 10 T
2
L fan-out capability
• Fits standard 40-pin DIP socket
• Auto-insertable
FUNCTIONAL DESCRIPTION
The PDU17F-series device is a 7-bit digitally programmable delay line.
The delay, TD
A
, from the input pin (IN) to the output pins (OUT, OUT/)
depends on the address code (A6-A0) according to the following formula:
TD
A
= TD
0
+ T
INC
* A
where A is the address code, T
INC
is the incremental delay of the device,
and TD
0
is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The
enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state
and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced
into LOW and HIGH states, respectively. The address is not latched and must remain asserted during
normal operation.
SERIES SPECIFICATIONS
• Programmed delay tolerance: 5% or 2ns,
whichever is greater
• Inherent delay (TD
0
): 13ns typical (OUT)
12ns typical (OUT/)
• Setup time and propagation delay:
Address to input setup (T
AIS
): 10ns
Disable to output delay (T
DISO
): 6ns typ. (OUT)
• Operating temperature: 0° to 70° C
• Temperature coefficient: 100PPM/°C (excludes TD
0
)
• Supply voltage V
CC
: 5VDC ± 5%
• Supply current: I
CCH
= 68ma
I
CCL
= 86ma
• Minimum pulse width: 8% of total delay
1997 Data Delay Devices
data
delay
devices, inc.
3
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
N/C
OUT/
OUT
EN/
GND
N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
GND
N/C
EN/
N/C
IN
N/C
GND
VCC
N/C
A0
A1
A2
VCC
N/C
A3
A4
A5
VCC
N/C
N/C
N/C
N/C
VCC
N/C
A6
N/C
N/C
PDU17F-xx
DIP
PDU17F-xxC5
Gull-Wing
PDU17F-xxM
Military DIP
PDU17F-xxMC5
Military Gull-Wing
PIN DESCRIPTIONS
IN Delay Line Input
OUT Non-inverted Output
OUT/ Inverted Output
A0-A6 Address Bits
EN/ Output Enable
VCC +5 Volts
GND Ground
DASH NUMBER SPECIFICATIONS
Part
Number
Incremental Delay
Per Step (ns)
Total Delay
Change (ns)
PDU17F-.5
.5 ± .3 63.5 ± 3.2
PDU17F-1
1 ± .5 127 ± 6.4
PDU17F-2
2 ± .5 254 ± 12.7
PDU17F-3
3 ± 1.0 381 ± 19.1
PDU17F-4
4 ± 1.0 508 ± 25.4
PDU17F-5
5 ± 1.5 635 ± 31.8
PDU17F-6
6 ± 1.5 762 ± 38.1
PDU17F-8
8 ± 2.0 1,016 ± 50.8
PDU17F-10
10 ± 2.0 1,270 ± 63.5
NOTE: Any dash number between .5 and 10 not
shown is also available.
PDU17F
Doc #97005 DATA DELAY DEVICES, INC. 2
1/14/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
APPLICATION NOTES
ADDRESS UPDATE
The PDU17F is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time,
T
OAX
, is required before the address lines can
change. This time is given by the following
relation:
T
OAX
= max { (A
i
- A
i-1
) * T
INC
, 0 }
where A
i-1
and A
i
are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required T
OAX
has elapsed.
A similar situation occurs when using the EN/
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the EN/ signal high and
the IN signal low for a time given by:
T
DISH
= A
i
* T
INC
Violation of this constraint may, depending on
the history of the input signal, cause spurious
signals to appear on the OUT pin. The
possibility of spurious signals persists until the
required T
DISH
has elapsed.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay
tolerance specifications and monotonicity are
guaranteed. The suggested conditions are
those for which signals will propagate through the
unit without significant distortion. The absolute
conditions are those for which the unit will
produce some type of output for a given input.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
T
DISO
T
OAX
T
AENS
T
ENIS
PW
IN
TD
A
PW
OUT
T
DISH
A6-A0
EN/
IN
OUT
OUT/
Figure 1: Timing Diagram
A
i-1
A
i
T
SKEW
T
AIS