PDU138
Doc #02004 DATA DELAY DEVICES, INC. 1
5/6/02 3 Mt. Prospect Ave. Clifton, NJ 07013
3-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU138)
FEATURES PACKAGES
• Digitally programmable in 8 delay steps
• Monotonic delay-versus-address variation
• Precise and stable delays
• Input & outputs fully TTL interfaced & buffered
• 10 T
2
L fan-out capability
• Fits standard 16-pin DIP socket
• Auto-insertable
FUNCTIONAL DESCRIPTION
The PDU138-series device is a 3-bit digitally programmable delay line.
The delay, TD
A
, from the input pin (IN) to the output pin (OUT) depends on
the address code (A2-A0) according to the following formula:
TD
A
= TD
0
+ T
INC
* A
where A is the address code, T
INC
is the incremental delay of the device,
and TD
0
is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns
through 50ns, inclusively. The enable pin (EN/) is held LOW during normal
operation. When this signal is brought HIGH, OUT is forced into the LOW
state. The address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
• Total programmed delay tolerance: 5% or 1ns,
whichever is greater
• Inherent delay (TD
0
): 7ns typical (OUT)
• Setup time and propagation delay:
Address to input setup (T
AIS
): 12ns typ.
Disable to output delay (T
DISO
): 12ns typ.
• Operating temperature: 0° to 70° C
• Temperature coefficient: 100PPM/°C (excludes TD
0
)
• Supply voltage V
CC
: 5VDC ± 5%
• Supply current: I
CCH
= 45ma
I
CCL
= 20ma
• Minimum pulse width: 20% of total delay
2002 Data Delay Devices
data
delay
devices,
inc.
3
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
N/C
N/C
N/C
IN
OUT
N/C
EN/
GND
VCC
N/C
N/C
N/C
N/C
A0
A1
A2
PDU138-xx DIP
PDU138-xxM Military DIP
PIN DESCRIPTIONS
IN Delay Line Input
OUT Non-inverted Output
A2 Address Bit 2
A1 Address Bit 1
A0 Address Bit 0
EN/ Output Enable
VCC +5 Volts
GND Ground
DASH NUMBER SPECIFICATIONS
Part
Number
Incremental Delay
Per Step (ns)
Total Delay
Change (ns)
PDU138-.5
.5 ± .3 3.5 ± 1.0
PDU138-1
1 ± .4 7 ± 1.0
PDU138-2
2 ± .4 14 ± 1.0
PDU138-5
5 ± .6 35 ± 1.8
PDU138-10
10 ± 1.0 70 ± 3.5
PDU138-12
12 ± 1.2 84 ± 4.2
PDU138-15
15 ± 1.3 105 ± 5.3
PDU138-20
20 ± 1.5 140 ± 7.0
PDU138-40
40 ± 2.0 280 ± 14.0
PDU138-50
50 ± 2.5 350 ± 17.5
NOTE: Any dash number between .5 and 50 not
shown is also available.
PDU138
Doc #02004 DATA DELAY DEVICES, INC. 2
5/6/02 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
APPLICATION NOTES
ADDRESS UPDATE
The PDU138 is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time, T
OAX
,
is required before the address lines can change.
This time is given by the following relation:
T
OAX
= max { (A
i
- A
i-1
) * T
INC
, 0 }
where A
i-1
and A
i
are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT pin.
The possibility of spurious signals persists until
the required T
OAX
has elapsed.
A similar situation occurs when using the EN/
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the EN/ signal high and the
IN signal low for a time given by:
T
DISH
= A
i
* T
INC
Violation of this constraint may, depending on the
history of the input signal, cause spurious signals
to appear on the OUT pin. The possibility of
spurious signals persists until the required T
DISH
has elapsed.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay tolerance
specifications and monotonicity are guaranteed.
The suggested conditions are those for which
signals will propagate through the unit without
significant distortion. The absolute conditions
are those for which the unit will produce some
type of output for a given input.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will remain
constant from pulse to pulse if the input pulse
width and period remain fixed. In other words,
the delay of the unit exhibits frequency and pulse
width dependence when operated beyond the
recommended conditions. Please consult the
technical staff at Data Delay Devices if your
application has specific high-frequency
requirements.
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
T
DISO
T
OAX
T
AENS
T
ENIS
PW
IN
TD
A
PW
OU
T
DISH
A2-A0
EN/
IN
OUT
Figure 1: Timing Diagram
A
i-1
A
i
T
AIS