Xilinx Answer 71210 – PS/PL PCIe Debug Guide 1

Xilinx Answer 71210

Xilinx PCI Express (PS-PCIe/PL-PCIe) Drivers Debug Guide

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Introduction

This document provides a detailed information on resources for debugging drivers pertaining to the Zynq® UltraScale+™

MPSoC controller for the integrated block for PCI Express (PS-PCIe), DMA Subsystem for PCI Express (Bridge Mode) in

Zynq UltraScale+ MPSoC (XDMA PL-PCIe) and AXI Bridge for PCI Express (AXI PCIe Gen2) in 7 Series devices.

To ease development of a PCIe system using Xilinx PCI Express IPs, Xilinx has created Wiki pages detailing the available

reference designs, Device Tree and Drivers for Root Port configuration with PS-PCIe, XDMA PL-PCIe and AXI PCIe Gen2.

This document provides links to relevant wiki pages in different sections.

Debugging designs related to PS-PCIe could be challenging especially because of the integrated nature of the IP, it doesn’t

provide much visibility inside the IP in comparison to other base PCI Express IPs that Xilinx provides. In such scenarios, it

would be necessary to probe different registers to troubleshoot a design. A list of such gotchas, registers, and debugging

tips have been provided to help users to debug their designs.

There are three separate PCIe host drivers for the following IPs:

 Zynq UltraScale+ MPSoC controller for the integrated block for PCI Express (PS-PCIe)

 DMA Subsystem for PCI Express configured as Root Port in PL of Zynq UltraScale+ MPSoC (XDMA PL-PCIe)

 AXI Bridge for PCI Express (AXI PICe Gen2) for Zynq-7000 devices.

The debugging approach for each IP should be considered differently. This document provides clear distinction between

PS-PCIe, XDMA PL-PCIe and AXI PCIe Gen2.

PS-PCIe Controller Overview

UG1085 provides details on the integrated block for PCI Express v2.1 compliant AXI-PCIe Bridge and DMA modules (PS-

PCIe) available in the Zynq UltraScale+ MPSoC. It supports Gen1/Gen2 rates at x1/x2/x4 link widths configured either as

Endpoint or Root Port.

The AXI streaming and sideband signals between the AXI-PCIe Bridge and the integrated block for PCI Express are not

directly accessible. Every PCIe transfer initiated in the AXI domain passes through the AXI-PCIe Bridge.