Revision D, 08.01.2004 Page 1 of 6
ANALOG IP BLOCK
LVDS_TX - CMOS LVDS Transmitter
DATA SHEET
FEATURES
LVDS_TX area: 0.184mm
2
,
LVDS_TX size: x = 533µm y = 345.7µm
TXBIAS area: 0.08mm
2
,
TXBIAS size: x = 332.4µm y = 239.3µm
3.3V ±10% supply voltage
±350mV differential signaling
1Gb/s maximum transmission speed
800ps maximum propagation delay
Power dissipation 33mW at 3.3V, static, without
TXBIAS
Junction temperature –40 - 125°C
Compatible with IEEE 1596.3 SCI LVDS standard
Internal 100Ω termination resistor
High capacitive loads driving capability:
10pF @ 1Gb/s
Power down mode
DESCRIPTION
The LVDS_TX is a differential line driver designed for
applications requiring high data rates. The device supports
data rates up to 1Gb/s (500MHz).
The LVDS_TX accepts CMOS input levels and translates them
to low voltage (350mV) differenti
al output signals, which
provides low EMI even at high frequencies.
With the companion line receiver (LVDS_RX ) it provides a new
alternative to high power pseudo-
ECL devices for high speed
applications.
The LVDS_TX requires the cell TXBIAS for biasing.
TXBIAS
can drive up to 3 LVDS_TX cells. An external voltage reference
must be used.
The LVDS_TX is designed as pad cell and has the same high
(y-
size) as austriamicrosystems AG standard pad cells with
separated substrate.
PROCESS
C35B3 (0.35um)
Datasheet: LVDS_TX - C35
Revision D, 08.01.2004 Page 2 of 6
TECHNICAL DATA FOR LVDS_TX
(T
junction
= −40 to 125°C, VDDA = 3.0V to 3.6V, VSSA = VSUB = 0V, VREF = 1.25V, PD = low, receiver input termination resistance
R
L
= 100Ω, unless otherwise specified)
DC CHARACTERISTICS
Symbol Parameter Conditions Min Typ Max Units
V
OD
Differential Output Swing
V
OD
= |VOUTP – VOUTN|
250 350 450 mV
V
OCM
Common Mode Output Voltage
V
OCM
= (VOUTP + VOUTN) / 2
1.11 1.25 1.37 V
V
OH
Output Voltage High 1.425 1.60 V
V
OL
Output Voltage Low 0.88 1.075 V
V
IH
Input Voltage High V
V
IL
Input Voltage Low
CMOS levels
V
AC CHARACTERISTICS
Symbol Parameter Conditions Min Typ Max Unit
t
PLHD
Different. Propagation Delay Low to High
C
load
= 10pF
1)
400 ps
t
PHLD
Different. Propagation Delay High to Low
C
load
= 10pF
1)
400 ps
t
SKD1
Differential Pulse Skew |t
PLHD
– t
PHLD
|
2)
C
load
= 10pF @1Gb/s
1)
70 ps
t
SKD2
Differential Channel to Channel Skew
C
load
= 10pF @1Gb/s
1)
80 ps
t
TLHD
Differential Output Rise Time
C
load
= 10pF
1) 3)
550 ps
t
THLD
Differential Output Fall Time
C
load
= 10pF
1) 3)
550 ps
t
PZH
Power Up Time High-Z to High
C
load
= 10pF
300 500 ns
t
PZL
Power Up Time High-Z to Low
C
load
= 10pF
300 500 ns
C
load
Load Capacitance @1Gb/s 14 pF
C
in
Input Capacitance 1 2 pF
f
MAX
Maximum Operating Frequency
4)
500 MHz
T
XS
Transmission Rate 1000 Mb/s
POWER REQUIREMENTS
Symbol Parameter Conditions Min Typ Max Unit
I
OS
Output Short Circuit Current Outputs shorted to
VSSA
16 25 mA
I
OSD
Differential Output Short Circuit Current VOUTP and VOUTN
shorted, V
OD
= 0V
8 12 mA
I
CCDC
DC Current Consumption No TXBIAS 10 15 mA
I
CCAC
AC Current Consumption
C
load
= 10pF @1Gb/s,
no TXBIAS
16 25 mA
I
CCPD
Power Down Current Consumption
5)
PD = high, no TXBIAS
10 µA
P
diss_DC
DC Power Consumption No TXBIAS 33 54 mW
P
diss_AC
AC Power Consumption No TXBIAS 52.8 90 mW
P
diss_PD
Power Consumption in Power Down Mode
PD = high, no TXBIAS
36 µW
1)
Including the package: SOIC28, pins 5–10 or 19–24 for VOUTP and VOUTN
2)
t
SKD1
is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
same channel
3)
Specified at 20% and 80% of the output voltage (IEEE 1596.3 SCI LVDS standard)
4)
f
MAX
generator input conditions: t
r
= t
f
< 500ps, 50% duty cycle, output criteria: V
OD
> 250mV
5)
Static input signals: VINP = VDDA, VINN = VSSA