Replacing the Cypress CY14B256LA-ZS25 nvSRAM

with Everspin MR256A08BMA35 MRAM

Application Note EST 02058, 8/2015

Replacing the Cypress CY14B256LA nvSRAM with Ever spin

MR256A08B MRAM

GENERAL CONSIDERATIONS for REPLACING nvSRAM with MRAM

Every write with an MRAM is inst antly non-volatile f or at least 20 years . There is no t ransfer

of data from a volatile to a non-volatile memory cell, no external capacitors or back up

batteries. The elimination of external components, highly reliable data retention, and 35ns

SRAM compatible READ/WRITE speed makes MRAM a viable candidate for reducing

system cost without compromising system performance.

EVERSPIN MRAM MEMORY

Everspin is the global leader in commercially available MRAM technology and Everspin

MRAM products are present in hundreds of applications demanding high-speed, reliable,

non-volat il e mem or y.

MR256A08B COMPARISON TO CY14B256LA

The Everspi n MRAM solution pr ovides:

• Always non-volatile. No unr eliable capac itor dependent backup cycles

• No V

CAP

or V

BATT

required

• Immediate (<1ns) Power-off with no loss of dat a

• No complex Software ST ORE/RECA LL r outines

• Fast S tart-up time (2ms vs. 20ms)

• Unlimited Read and Write cycles. No Wear-out Concerns

• 20-Year Data Ret ention with No Cycling De pendence

• Fewer components means smaller des ign footpr int and lower t otal BOM cost

• Directly replaces the Cypres s nvSRAM

COMPATIBILITY

The Everspin MR256A08BCYS (44-TSOP2) memory is pin and timing compatible with the

Cypress CY 14B 256LA-ZS.

TIMING COMPATIBILITY

Both Everspin MRAM and nvSRA M have st andar d, c om patible asynchr onous SRAM t im ing.

The MRAM h o we ver , retains dat a ev en at power of f f or an indef init e per iod of t im e and over

temperature cycling. With a 35 ns read/write cycle time, the MRAM is compatible with

similar nvSRAM speed gr ade options.

It is important to note that the Everspin MR256A08B device requires a minimum of 12ns

hold time from Write Enable (and Chip Enable) high to Address invalid (Please see T

WHAX

Replacing the Cypress CY14B256LA-ZS25 nvSRAM

with Everspin MR256A08BMA35 MRAM

Application Note EST 02058, 8/2015

and T

EHAX

in the MR256A08B data sheet available here.) Most microprocessors can

accommodate this Hold time.

PIN COMPATIBILITY

• 256Kb organized in the 32Kx 8 c onfigurat i on

• 3.3 volt nominal operation

• Standard SRAM paralle l address pins (A0-14)

• Standard byte-wide, bidirectional data pins (D Q0-7)

• Standard control signals (/E , /W, /G)

The MR256A08B does not require an external capacitor and other associated passive

components required b y the CY14B256LA-xx devices.

The primary differences bet ween the C ypress a nd Everspin devices are the t wo pins on the

nvSRAM: V

CAP

and /HSB. These pins are used to support the nvSRAM backup cycle and

are not requir ed for operation of the MRAM.

CAP

A capacitor is required on the V

CAP

pins (Pin 30 on the TSOP2) on nvSRAM devices.

Everspin assigns a “Do not connect” (DC) to the corresponding pins on the MRAM. W hen

replacing the Cypress nvSRAM with t he Eversp in MRAM, it is recomm ended that this pin be

either lef t f loating or kept at V

. If a capacitor or V

is connected t o this pin, it will have no

effect on MRAM operation. However, the device may draw more current than if this pin is

pulled to V

or left floating.

/HSB pin

The /HSB pin of the nvSRAM (Pin 44 of the TSOP2) is used to either initiate a Hardware

Store or indicate a Hardware Store is in process. The corresponding pin on the MRAM is

recommended “Do not connec t” with the MRAM 44 pin TSOP2.

On pin 44 on the MRAM TSOP2 package, the MRAM has a static pull-down to V

Consequently, a Host processor should not expect the MRAM to drive this pin to a high

state.