PAC5223 User Guide
Power Application Controller
TABLE OF CONTENTS
1. Styles and Formatting Conventions................................................................................................................. 25
1.1. Overview.................................................................................................................................................. 25
1.2. Number Representation........................................................................................................................... 25
1.3. Formatting Styles..................................................................................................................................... 25
2. Memory and Register Map............................................................................................................................... 26
2.1. Memory Map............................................................................................................................................ 26
2.2. Register Map............................................................................................................................................ 27
3. Information Block............................................................................................................................................. 39
3.1. Register.................................................................................................................................................... 39
3.1.1. Register Map.................................................................................................................................... 39
3.1.2. ROSC11........................................................................................................................................... 39
3.1.3. VREFV............................................................................................................................................. 39
3.1.4. ADCGAIN......................................................................................................................................... 40
3.1.5. ADCOFF.......................................................................................................................................... 40
3.1.6. FTTEMP........................................................................................................................................... 40
3.1.7. TEMPS............................................................................................................................................. 40
3.1.8. CLKREF........................................................................................................................................... 40
3.1.9. DIEREV............................................................................................................................................ 40
3.1.10. PACIDR.......................................................................................................................................... 40
3.2. Details of Operation................................................................................................................................. 41
3.2.1. Overview.......................................................................................................................................... 41
4. System Clock Control....................................................................................................................................... 42
4.1. Register.................................................................................................................................................... 42
4.1.1. Register Map.................................................................................................................................... 42
4.1.2. CCSCTL........................................................................................................................................... 42
4.1.3. PLLCTL............................................................................................................................................ 43
4.1.4. OSCCTL.......................................................................................................................................... 43
4.1.5. XTALCTL.......................................................................................................................................... 43
4.2. Details of Operation................................................................................................................................. 44
4.2.1. Block Diagram.................................................................................................................................. 44
4.2.2. Configuration.................................................................................................................................... 44
4.2.3. ROSC............................................................................................................................................... 45
4.2.4. CLKREF........................................................................................................................................... 45
4.2.5. XTAL................................................................................................................................................ 45
4.2.6. EXTCLK........................................................................................................................................... 45
4.2.7. PLL................................................................................................................................................... 45
4.2.8. FRCLK............................................................................................................................................. 46
4.2.9. FCLK................................................................................................................................................ 46
4.2.10. HCLK............................................................................................................................................. 46
4.2.11. ACLK.............................................................................................................................................. 46
4.2.12. Clock Gating................................................................................................................................... 46
5. Watchdog Timer............................................................................................................................................... 47
5.1. Register.................................................................................................................................................... 47
5.1.1. Register Map.................................................................................................................................... 47
5.1.2. WDTCTL.......................................................................................................................................... 47
5.1.3. WDTCDV......................................................................................................................................... 48
5.1.4. WDTCTR......................................................................................................................................... 48
5.2. Details of Operation................................................................................................................................. 49
5.2.1. Block Diagram.................................................................................................................................. 49
5.2.2. Configuration.................................................................................................................................... 49
5.2.3. Watchdog Timer............................................................................................................................... 49
- 2 - Rev 15‒July 21, 2017