Key features Applications

• 2.4 GHz transceiver

•

-96 dBm sensitivity in Bluetooth

low energy mode

• 1 Mbps, 2 Mbps supported data rates

• TX power -20 to +4 dBm in 4 dB steps

•

Single-pin antenna interface

• 5.3 mA peak current in TX (0 dBm)

• 5.4 mA peak current in RX

• RSSI (1 dB resolution)

•

ARM

Cortex

-M4 32-bit processor with FPU, 64 MHz

•

215 EEMBC CoreMark

score running from flash memory

• 58 μA/MHz running from flash memory

• 51.6 μA/MHz running from RAM

• Data watchpoint and trace (DWT), embedded trace macrocell (ETM), and

instrumentation trace macrocell (ITM)

• Serial wire debug (SWD)

• Trace port

• Flexible power management

• Supply voltage range 1.7 V–3.6 V

• Fully automatic LDO and DC/DC regulator system

• Fast wake-up using 64 MHz internal oscillator

• 0.7 μA at 3 V in OFF mode

• 1.0 μA at 3 V in OFF mode with 32 kB RAM retention

• 1.9 μA at 3 V in ON mode, no RAM retention, wake on RTC

• Memory

• 512 kB flash/64 kB RAM

• 256 kB flash/32 kB RAM

• Nordic SoftDevice ready

• Support for concurrent multi-protocol

• Type 2 near field communication (NFC-A) tag with wakeup-on-field and touch-

to-pair capabilities

• 12-bit, 200 ksps ADC - 8 configurable channels with programmable gain

• 64 level comparator

• 15 level low power comparator with wakeup from System OFF mode

• Temperature sensor

• 32 general purpose I/O pins

• 3x 4-channel pulse width modulator (PWM) units with EasyDMA

• Digital microphone interface (PDM)

• 5x 32-bit timers with counter mode

• Up to 3x SPI master/slave with EasyDMA

• Up to 2x I2C compatible 2-Wire master/slave

• I2S with EasyDMA

• UART (CTS/RTS) with EasyDMA

• Programmable peripheral interconnect (PPI)

• Quadrature decoder (QDEC)

• AES HW encryption with EasyDMA

• Autonomous peripheral operation without CPU intervention using PPI and

EasyDMA

• 3x real-time counter (RTC)

• External system

• Single crystal operation

• On-chip balun (single-ended RF)

• Few external components

• Package variants

• QFN48 package, 6 × 6 mm

• WLCSP package, 3.0 × 3.2 mm

• Internet of Things (IoT)

• Home automation

• Sensor networks

• Building automation

• Industrial

• Retail

• Personal area networks

• Health/fitness sensor and monitor devices

• Medical devices

• Key fobs and wrist watches

• Interactive entertainment devices

• Remote controls

• Gaming controllers

• Beacons

• A4WP wireless chargers and devices

• Remote control toys

• Computer peripherals and I/O devices

• Mouse

• Keyboard

• Multi-touch trackpad

• Gaming

nRF52832 Product Specification v1.1

Applications

Contents

Page 2

Contents

1 Revision history................................................................................... 9

2 About this document............................................................................................ 10

2.1 Peripheral naming and abbreviations................................................................................... 10

2.2 Register tables...................................................................................................................... 10

2.3 Registers............................................................................................................................... 11

3 Block diagram........................................................................................................12

4 Pin assignments.................................................................................................... 13

4.1 QFN48 pin assignments....................................................................................................... 13

4.2 WLCSP ball assignments..................................................................................................... 15

4.3 GPIO usage restrictions........................................................................................................17

5 Absolute maximum ratings.................................................................................. 19

6 Recommended operating conditions.................................................................. 20

7 CPU......................................................................................................................... 21

7.1 Floating point interrupt.......................................................................................................... 21

7.2 Electrical specification...........................................................................................................21

7.3 CPU and support module configuration................................................................................22

8 Memory................................................................................................................... 23

8.1 RAM - Random access memory...........................................................................................23

8.2 Flash - Non-volatile memory.................................................................................................24

8.3 Memory map......................................................................................................................... 24

8.4 Instantiation........................................................................................................................... 24

9 AHB multilayer.......................................................................................................26

9.1 AHB multilayer priorities........................................................................................................26

10 EasyDMA.............................................................................................................. 27

10.1 EasyDMA array list............................................................................................................. 28

11 NVMC — Non-volatile memory controller.........................................................29

11.1 Writing to Flash...................................................................................................................29

11.2 Erasing a page in Flash..................................................................................................... 29

11.3 Writing to user information configuration registers (UICR)................................................. 29

11.4 Erasing user information configuration registers (UICR).................................................... 29

11.5 Erase all.............................................................................................................................. 30

11.6 Cache.................................................................................................................................. 30

11.7 Registers............................................................................................................................. 30

11.8 Electrical specification.........................................................................................................33

12 BPROT — Block protection................................................................................34

12.1 Registers............................................................................................................................. 34

13 FICR — Factory information configuration registers.......................................43

13.1 Registers............................................................................................................................. 43

14 UICR — User information configuration registers........................................... 54

14.1 Registers............................................................................................................................. 54

15 Peripheral interface............................................................................................. 68

15.1 Peripheral ID....................................................................................................................... 68

15.2 Peripherals with shared ID..................................................................................................68

15.3 Peripheral registers............................................................................................................. 69

15.4 Bit set and clear..................................................................................................................69

15.5 Tasks...................................................................................................................................69

15.6 Events..................................................................................................................................70

15.7 Shortcuts............................................................................................................................. 70

15.8 Interrupts............................................................................................................................. 70