WP389 (v1.3) January 5, 2015 www.xilinx.com 1
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This white paper describes several aspects of power
related to the Xilinx® 28 nm 7 series FPGAs and
Zynq®-7000 devices, including the TSMC 28 nm
high-k metal gate (HKMG), high performance, low
power (28 nm HPL or 28 HPL) process choice.
The power benefits afforded by the 28 HPL process
and its usefulness across Xilinx's full product
offerings is described as well as the architectural
innovations and features for power reduction across
the dimensions of static power, dynamic power, and
I/O power.
White Paper: 7 Series FPGAs
WP389 (v1.3) January 5, 2015
Lowering Power at 28 nm
with Xilinx 7 Series Devices
By: Jameel Hussein, Matt Klein, and Michael Hart
2 www.xilinx.com WP389 (v1.3) January 5, 2015
Introduction
Introduction
Power consumption in programmable devices has become a primary factor for in
device selection. Whether the concern is absolute power consumption, usable
performance, battery life, thermal challenges, or reliability, power consumption is at
the center of it all. Xilinx has been focused on reducing power consumption for many
years, starting with development of Virtex®-4 FPGAs, in which significant static
power reduction was achieved by the use of triple oxide. In addition, the Virtex-4
devices offered customers a way to model the effects of temperature on static power in
FPGAs (see
WP221, Static Power and the Importance of Realistic Junction Temperature Analysis).
Xilinx has continued to study and implement many different power reduction
strategies, which span process changes and improvements, architecture changes,
voltage scalable products, and software power optimization strategies.
For the Xilinx 7 series devices (Artix®-7, Kintex®-7, Virtex-7 devices) and Zynq®-7000
devices, all of these strategies were evaluated based on their impact on static power,
dynamic power, and I/O power. There was an additional examination of risk in the
case of new technologies, time to market for the implementation, performance impact,
software impact, and die area, which can be equated to cost. This white paper
describes several aspects of power related to Xilinx’s newest 28 nm 7 series devices,
including: the 28 HPL process chosen by Xilinx; benefits on power and usefulness
across all Xilinx product offerings; and the architectural innovations and features for
power reduction across the dimensions of static power, dynamic power, and I/O
power.
Choosing the Right Process Technology
Prior to product release, at every process node, Xilinx spends several years
researching innovative process technology and determining how well suited the
various options are for programmable device architectures. The research focuses on
performance, power, and ease of manufacture. TSMC offers three processes at 28 nm:
the 28 LP process, the 28 HP process, and the 28 HPL process. The best choice for the
Xilinx 7 series FPGAs and Zynq-7000 devices is the 28 HPL process, with power and
performance being significant driving forces in the decision (see Xilinx Press Release
,
Xilinx Picks 28 nm High-Performance, Low-Power Process
).
In the definition stages of the 7 series devices, Xilinx considered all possible 28 nm
process technologies.Very early, Xilinx recognized the advantages of HKMG transistor
technology for programmable device applications and worked closely with the
foundry partner to define and develop this technology. HKMG enables significant
intrinsic performance improvement (over 40 nm and traditional Polysilicon/Silicon
Oxy-Nitride (Poly/SiON)) and creates the opportunity for a scalable, optimized
architecture to cover both high-performance and low-cost FPGAs. A trade-off of some
of the intrinsic performance gain for lower power mitigates some of the static power
problems reported by other companies at 40 nm.