Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Features

• Supports output wander and jitter generation

specifications for GR-253-CORE OC-3 and G.813

STM-1 SONET/SDH interfaces

• Accepts two input references and synchronizes to

any combination of 2 kHz, 8 kHz, 1.544 MHz,

2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz

inputs

• Provides a 19.44 MHz (SONET/SDH) clock output

• Provides an 8 kHz framing pulse and a 2 kHz

multi-frame pulse

• Provides automatic entry into Holdo ver and return

from Holdover

• Hitless reference switching between any

combination of valid input reference frequencies

• Provides lock and accu rate re fere nce fail

indication

• Loop filter bandwidth of 29 Hz or 14 Hz

• Less than 24 ps

rms

intrinsic jitter on the 19.44 MHz

output clock, compliant with GR-253-CORE OC-3

and G.813 STM-1 specifications

• Less than 0.5 ns

intrinsic jitter on output frame

pulses

• External master clock source: clock oscillator or

crystal

• Simple hardware control interface

Applications

• Line card synchronization for SONET/SDH

systems

Description

The ZL30108 SONET/SDH network interface digital

phase-locked loop (DPLL) provides timing and

synchronization for SONET/SDH network interface

cards.

The ZL30108 generates a SONET/SDH clock and

framing signals that are phase locked to one of two

backplane or network references. It helps ensure

system reliability by monitoring its references for

frequency accuracy and stability and by maintaining

tight phase alignment between the input reference

clock and clock outputs.

The ZL30108 output clock’s wander and jitter

generation are compliant with GR-253-CORE OC-3

and G.813 STM- 1 specifications.

May 2009

Ordering Information

ZL30108LDA 32 Pin QFN Tubes, Bake & Drypack

ZL30108LDG1 32 Pin QFN* Trays, Bake & Drypack

*Pb Free Matte Tin

-40°C to +85°C

ZL30108

SONET/SDH

Network Interface DPLL

Data Sheet

Figure 1 - Functional Block Diagram

Reference

Monitor

Mode

Control

Virtual

Reference

TIE

Corrector

Enable

State Machine

Frequency

Select

TIE

Corrector

Circuit

MODE_SEL

REF1

RST

REF_SEL

TIE_CLR

OSCoOSCi

Master Clock

REF0

LOCK

REF_FAIL0

REF_FAIL1

DPLL

MUX

Frequency

Synthesizer

F8ko

C19o

F2ko

OOR_SEL

ZL30108 Data Sheet

Zarlink Semiconductor Inc.

1.0 Change Summary

Changes from March 2006 Issue. Page, section, figure and table numbers refer to this current issue.

Changes from November 2005 Issue. Page, section, figure and table numbers refer to this current issue.

Changes from July 2005 Issue. Page, section, figure and table numbers refer to this current issue.

Changes from October 2004 Issue to July 2005 Issue. Page, section, figure and table numbers re fer to this issue.

Page Item Change

1 Ordering Information Updates to Packaging Information. Added new packaging

variants. Added Section 9.0.

Page Item Change

1 Ordering Information Updated Ordering Information.

Page Item Change

1 Features Changed description for hitless reference switching.

18 Section 7.1 Removed power supply decoupling circuit and included

reference to synchronizer power supply decoupling application

note.

Page Item Change

6RST

pin Specified clock and frame pulse outputs forced to high

impedance.

20 Section 7.4 Corrected time-constant of example reset circuit.

21 Table “DC Electrical Characteristics*“ Corrected Schmitt trigger levels.

25 Table “Performance Characteristics* -

Functional“

Specified TIE_CLR

=1 in Lock Time conditions.