Zarlink Semiconductor Inc.

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Contents

1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

2.0 Master/Slave Design Considerations ATCA

Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

3.0 Implementing Redundancy Protection using

the ZL30116/121 . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

3.1 Features of the ZL30116/121 to Support the

ATCA Master Timing Function . . . . . . . . . . . . . . . . . .3

3.2 Features of the ZL30116/121 to Support the

Slave Timing Function . . . . . . . . . . . . . . . . . . . . . . . 4

4.0 Operating the ZL30116/121 in Master/Slave

Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4.1 Master Configuration and Operation . . . . . . .7

4.2 Slave Configuration and Operation . . . . . . . .8

5.0 ATCA Central Timing Card Block Diagram . . .9

6.0 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.0 Introduction

A common architecture in telecommunications

products is comprised of 2 central control cards and

multiple line cards that communicate over a common

backplane. The control cards will typically include

features such as a system control processor, switching

fabric and system timing. For the purposes of this

application note we will be looking at the system timing

architecture of one such system.

The Advance Telecom Computing Architecture (ATCA)

is an open standard optimized for next-generation

telecommunications equipment. It provides a common

platform that allows telecom equipment manufacturers

to develop modular and interoperable hardware and

software. A carrier grade solution can be developed

using standard hardware and software building blocks

from a variety of vendors, thereby reducing the cost

and development time of telecom equipment.

This application note will discuss an implementation of

a redundant timing solution in an ATCA system using a

centralized architecture. This timing architecture is

commonly called Master/Slave. In this configuration as

shown in Figure 1, the Master (Active) Timing card is

synchronized to an external network reference and the

Slave (Redundant) timing card is synchronized to the

Master. The result is 2 sets of identical redundant

phase aligned system clocks for use by the system’s

line cards. In the case of a failure on the Master timing

card, the Slave card will seamlessly assume control of

the system and become the Master without causing

any disruptions to the system.

For an introduction to the ATCA Synchronization

interface and it’s centralized timing architecture visit

the Zarlink website at

http://timing.zarlink.com/assets/ATCATimingWhitepape

r_Part2.pdf

2.0 Master/Slave Design

Considerations ATCA Systems

Figure 1 shows the basic architecture for a redundant

centralized timing solution in an ATCA system. It

shows 2 Central Timing cards, each containing a

ZL30116/121 Network synchronizer, providing a

redundant set of system clocks to the ATCA

synchronization backplane. The Master Timing card,

takes an network reference from either an external

source such as a BITS or SSU clock or a clock from

one of the CLK3 ATCA buses, which is typically a

recovered line clock from one of the systems linecards.

The master is responsible for providing all standards

compliant network level synchronization. The slave

card locks itself to the output of the master card and

tracks it, ensuring that the 2 pairs of system clocks

remain aligned on the backplane. The main

considerations for choosing a timing solution for this

application are as follows:

• The Timing Card must be able to be configured as

either the master or the slave, it must also be able

to seamlessly transition from one to the other

without causing disruptions downstream on the

linecards.

• The timing card must be able to be configured to

drive and receive either the A or B set of system

clock buses.

• When operating as a master, the card must be

able to provide Stratum 3 level network

synchronization.

• When operating as a slave, the card must be able

to align its output clock to much the phase of the

master clocks within +/-10 ns. It must therefore be

able to compensate for the static misalignment

caused by buffer and trace delays, as well as the

dynamix misalignment caused by jitter/wander

and or transients on the master clock.

June 2006

ZLAN-200

Applications of the ZL30116/121

Master Slave Configuration in ATCA

Systems

Application Note