This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.4 / July 2006 1

HY5PS12421(L)F

HY5PS12821(L)F

HY5PS121621(L)F

512Mb DDR2 SDRAM

HY5PS12421(L)F

HY5PS12821(L)F

HY5PS121621(L)F

Rev. 1.4 / July 2006 2

1HY5PS12421(L)F

HY5PS12821(L)F

HY5PS121621(L)F

Revision History

Rev. History Draft Date

0.0

Preliminary

Apr.2003

0.1

Changed Some Description & IDD Spec

Jun. 2003

0.2

Editorial clean up, Fixed CL3~6 & AL0~5, Defined IDD Specifications,

Added Package outline, added Self -Refresh High temperature Entry, changed tRAS

spec. for DDR2 400

Dec. 2003

1.0

Transferred Functional description, command truth table pages and Some contents

of Operating conditions to <Device Operation>

Jul. 2004

Modified IDD specifications.

Nov. 2004

Changed IDD Spec.(IDD2P & IDD6)

Feb. 2005

1.1

Changed IDD6(L) spec.

Mar. 2005

1.2

IDD3P-S update

Apr. 2005

1.3

Typo Corrected

May 2006

1.4

Corrected typo, and removed improper note in ODT DC spec.

July 2006