This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev 04 / May . 2001 Hynix Semiconductor
HY62WT08081E Series
32Kx8bit CMOS SRAM
Document Title
32K x8 bit 2.7~5.5V Low Power Slow SRAM
Revision History
Revision No History Draft Date Remark
00 Initial Feb.05.2001 Preliminary
01 Revised Feb.13.2001 Final
- Change LL-Part Isb1 Limit @E.T/I.T, 4.5~5.5V
: 15uA => 20uA
02 Revised Feb.21.2001 Final
- Marking Information Change : SOP Type
- Voh Limit Change : 2.4V => 2.2V @2.7~3.6V
03 Changed Logo Apr.30.2001 Final
- HYUNDAI -> hynix
- Marking Information Change
04 Revised May.23.2001 Final
- Iccdr Limit Add : 2uA @40°C
HY62WT08081E Series
Rev 04 / May . 2001
2
DESCRIPTION
The HY62WT08081E is a high-speed, low power
and 32,786 X 8-bits CMOS Static Random
Access Memory fabricated using Hynix's high
performance CMOS process technology. It is
suitable for use in low voltage operation and
battery back-up application. This device has a
data retention mode that guarantees data to
remain valid at the minimum power supply
voltage of 2.0 volt.
FEATURES
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Low power consumption
• Battery backup(LL-part)
- 2.0V(min.) data retention
• Standard pin configuration
- 28 pin 600mil PDIP
-
28 pin 330mil SOP
- 28 pin 8x13.4 mm TSOP-I
(Standard)
Product Voltage
Speed Operation Standby Current(uA) Temperature
No. (V) (ns) Current(mA)
LL-part
(°C)
4.5~5.5
55/70 10 10 HY62WT08081E-C
2.7~3.6
70*/85 2 5
0~70(Normal)
4.5~5.5
55/70 10 20 HY62WT08081E-E
2.7~3.6
70*/85 2 8
-25~85(Extended)
4.5~5.5
55/70 10 20 HY62WT08081E-I
2.7~3.6
70*/85 2 8
-40~85(Industrial)
Note 1. Current value is max.
* 70ns is available with 30pF test load
PIN CONNECTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
/WE
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
/WE
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
/CS
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
/OE
A11
A9
A8
A13
/WE
Vcc
A14
A12
A7
A6
A5
A4
A3
I/O8
PDIP SOP TSOP-I(Standard)
PIN DESCRIPTION BLOCK DIAGRAM
Pin Name Pin Function
/CS Chip Select
/WE Write Enable
/OE Output Enable
A0 ~ A14 Address Inputs
I/O1 ~ I/O8 Data Input/Output
Vcc
Power(+5.0V)
Vss Ground
A14
COLUMN DECODER
A0
ROW DECODER
MEMORY ARRAY
512x512
SENSE AMP
OUTPUT BUFFER
I/O1
I/O8
ADD INPUT BUFFER
/CS
/OE
/WE
WRITE DRIVER
CONTROL
LOGIC