This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev 04 / Apr. 2001 Hynix Semiconductor
HY62CT08081E Series
32Kx8bit CMOS SRAM
Document Title
32K x8 bit 5.0V Low Power Slow SRAM
Revision History
Revision No History Draft Date Remark
00 Initial Nov.01.2000 Preliminary
01 Marking Information Add Dec.05.2000 Preliminary
Revised
- DC / AC Characteristics
- AC Test Condition Add : 5pF Test Load
02 Revised Feb.13.2001 Final
- Remove L-Part
- Change LL-Part Isb1 Limit @E.T/I.T
: 15uA => 20uA
03 Revised Feb.21.2001 Final
- Marking Information Change : SOP Type
04 Changed Logo Apr.30.2001 Final
- HYUNDAI -> hynix
- Marking Information Change
HY62CT08081E Series
Rev 04 / Apr. 2001
2
DESCRIPTION
The HY62CT08081E is a high-speed, low power
and 32,786 X 8-bits CMOS Static Random
Access Memory fabricated using Hynix's high
performance CMOS process technology. It is
suitable for use in low voltage operation and
battery back-up application. This device has a
data retention mode that guarantees data to
remain valid at the minimum power supply
voltage of 2.0 volt.
FEATURES
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Low power consumption
• Battery backup
- 2.0V(min.) data retention
• Standard pin configuration
-
28 pin 600mil PDIP
- 28 pin 330mil SOP
- 28 pin 8x13.4 mm TSOP-I
(Standard)
Product Voltage
Speed Operation Standby Current(uA) Temperature
No. (V) (ns) Current(mA)
LL
(°C)
HY62CT08081E-C
5.0 55/70/85
10 10 0~70(Normal)
HY62CT08081E-E 5.0 55/70/85
10 20 -25~85(Extended)
HY62CT08081E-I 5.0 55/70/85
10 20 -40~85(Industrial)
Note 1. Current value is max.
PIN CONNECTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
/WE
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
/WE
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
/CS
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
/OE
A11
A9
A8
A13
/WE
Vcc
A14
A12
A7
A6
A5
A4
A3
I/O8
PDIP SOP TSOP-I(Standard)
PIN DESCRIPTION BLOCK DIAGRAM
Pin Name Pin Function
/CS Chip Select
/WE Write Enable
/OE Output Enable
A0 ~ A14 Address Inputs
I/O1 ~ I/O8 Data Input/Output
Vcc
Power(+5.0V)
Vss Ground
A14
COLUMN DECODER
A0
ROW DECODER
MEMORY ARRAY
512x512
SENSE AMP
OUTPUT BUFFER
I/O1
I/O8
ADD INPUT BUFFER
/CS
/OE
/WE
WRITE DRIVER
CONTROL
LOGIC