EXAR Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com uarttechsupport@exar.com
DATA COMMUNICATIONS APPLICATION NOTE
DAN131
June 2002
EXARS ST16C650 A AND XR16C850 COMPARED WITH TI’S TL16C750
Author: PY
1.0 INTRODUCTION
This application note describes the major difference between Exar’s ST16C650A and XR16C850 with TI’s
TL16C750. These devices are very similar, with a few hardware, firmware-related and bus timing differences.
1.1 H
ARDWARE DIFFERENCES
The TI TL16C750 and Exar ST16C650A and XR16C850 are all available in the 44-pin PLCC package. The
ST16C650A and XR16C850 are also available in the 40-pin PDIP and 48-pin TQFP packages. Additionally,
the XR16C850 is available in the 52-pin QFP package. The TL16C750 is also available in the 64-pin SQFP
package. In the 44-pin PLCC package, the Exar and TI UARTs are pin-to-pin compatible if pin 34 of the
ST16C650A and XR16C850 is tied to VCC (pin 34 of the TL16C750 is not used).
The oscillator circuitry is similar, but there are some differences when using a crystal oscillator and when
using an external clock. See Figure 1below for the differences in the oscillator circuitry for a crystal oscillator .
When using an external clock input for frequencies greater than 24 MHz, the ST16C650A and XR16C850
will require a 2K pull-up resistor on the XTAL2 pin.
1.2 B
US TIMING DIFFERENCES
The TL16C750 requires that the -CS pin is asserted first before the -IOR or -IOW pin and the -IOR or -IOW
pin must be de-asserted before the -CS pin is de-asserted. During a read, the Exar UART can have either
the -CS or the -IOR signal asserted first and have either signal be de-asserted first. The signals are wire-
ORed in the Exar UART, therefore the second signal asserted will initiate the read cycle and the first signal
de-asserted terminates the read cycle. The same is true during a write for -CS and -IOW. The flexibility of
the Exar UARTs timing can be important in DSP, ARM, and MIPS designs.
F
IGURE 1. CRYS TAL OSCILLATOR CIRCUITRY DIFFERENCES
C1
10-30 pF
C2
40-60 pF
Y1
1.8432
MHz
to
16
MHz
R1
1.5 K
R2
1 ΜΩ
XTAL1 XTAL2
C1
22-47 pF
C2
22-47 pF
Y1
1.8432
MHz
to
24
MHz
R1
0-120
(Optional)
R2
500 ΚΩ − 1 ΜΩ
XTAL1 XTAL2
ST16C650A / XR16C850TL16C750
DATA COMMUNICATIONS APPLICATION NOTE
DAN131
2
1.3 FIRMWARE DIFFERENCES
1.3.1 Firmware Differences Between the ST16C650A and TL16C750
The internal registers in the ST16C650A offers more features than the TL16C750 with some differences:
R = Read-Only, W = Write-Only, R/W = Read/Write
T
ABLE 1: ST16C650A AND TL16C750 REGISTER SET DIFFERENCES
A2:A0 R/W ST16C650A TL16C750
LCR Bit-7 = 0
001 R/W Interrupt Enable Register (IER)
Bit-7 = Auto CTS# Interrupt Enable
Bit-6 = Auto RTS# Interrupt Enable
Bit-5 = Xoff Interrupt Enable
Interrupt Enable Register (IER)
Bit-7 = Not Used
Bit-6 = Not Used
Bit-5 = Low Power Mode
010 W FIFO Control Register (FCR)
Bit-5 = TX FIFO Trigger Level Select Bit-1
Bit-4 = TX FIFO Trigger Level Select Bit-0
FIFO Control Register (FCR)
Bit-5 = 64 Byte FIFO Enable
Bit-4 = Not Used
010 R Interrupt Status Register (ISR)
Bit-5 = Auto RTS/CTS Interrupt
Bit-4 = Xoff or Special Character Interrupt
Interrupt Status Register (ISR)
Bit-5 = 64 Byte FIFO Enabled
Bit-4 = Not Used
100 R/W Modem Control Register (MCR)
Bit-7 = BRG Prescaler
Bit-6 = Infrared Mode Enable
Bit-5 = INT Type Select
Bit-3 = OP2 Control/INT Output Enable in PC
Mode
Modem Control Register (MCR)
Bit-7 = Not Used
Bit-6 = Not Used
Bit-5 = Auto RTS/CTS Flow Control Enable
Bit-3 = OP2 Control
101 W Extra Feature Register (XFR)
RS485 Output Inversion, XonAny, LSR Inter-
rupt Immediate, RS485 Enable, IR RX Inver-
sion, IR Half-Duplex/Full-Duplex Mode
N/A
110 W Infrared T ransmit Pulsewid th Control Register
(IRPW)
N/A
LCR Bit-7 = 0, DLL = 0x00, DLM = 0x00
000 R Device Revision (DREV) N/A
001 R Device ID (DVID) N/A
LCR = 0xBF
010 R/W Enhanced Featu r e Registe r (EFR)
Auto RTS/CTS Enable, Enhanced Functions
Enable, Software Flow Control Select
N/A
100 R/W XON1 N/A
101 R/W XON2 N/A
110 R/W XOFF1 N/A
111 R/W XOFF2 N/A