EXAR Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com • uarttechsupport@exar.com
DATA COMMUNICATIONS APPLICATION NOTE
DAN132
June 2002
EXAR’S SINGLE CHANNEL UARTS COMPARED WITH TI’S TL16C550C
Author: PY
1.0 INTRODUCTION
This application note describes the major difference between Exar’s ST16C550, ST16C580, ST16C650A, and
XR16C850 with TI’s TL16C55 0C. These devices are very similar, with a few hardware, bus timing and firm-
ware-related differences.
1.1 H
ARDWARE DIFFERENCES
• The TI TL16C550C and Exar’s ST16C550, ST16C580, ST16C650A and XR16C850 are all available in the
48-pin TQFP, 44-pin PLCC, and 40-pin PDIP packages. Additionally, the XR16C850 is available in the 52-
pin QFP package. The Exar and TI UARTs are pin-to-pin compatible in the 40-pin PDIP package. In the 48-
pin TQFP and 44-pin PLCC packages, the Exar and TI UARTs are pin-to-pin compatible if pin 34 of the
ST16C650A and XR16C850 is tied to VCC (pin 34 of the TL16C550C, ST16C550, ST16C580 are not used).
• The oscillator circuitry is similar, but there are some differences when using a crystal oscillator and when
using an external clock. See Figure 1below for the differences in the oscillator circuitry for a crystal oscillator .
When using an external clock input for frequencies greater than 24 MHz, the Exar UARTs will require a 2K
pull-up resistor on the XTAL2 pin.
1.2 B
US TIMING DIFFERENCES
• The TL16C550C requires that the -CS pin is asserted first before the -IOR or -IOW pin and the -IOR or -IOW
pin must be de-asserted before the -CS pin is de-asserted. During a read, the Exar UART can have either
the -CS or the -IOR signal asserted first and have either signal be de-asserted first. The signals are wire-
ORed in the Exar UART, therefore the second signal asserted will initiate the read cycle and the first signal
de-asserted terminates the read cycle. The same is true during a write for -CS and -IOW. The flexibility of
the Exar UART timing can be important in DSP, ARM, and MIPS designs.
F
IGURE 1. CRYS TAL OSCILLATOR CIRCUITRY DIFFERENCES
C1
10-30 pF
C2
40-60 pF
Y1
1.8432
MHz
to
16
MHz
R1
1.5 KΩ
R2
1 ΜΩ
XTAL1 XTAL2
C1
22-47 pF
C2
22-47 pF
Y1
1.8432
MHz
to
24
MHz
R1
0-120 Ω
(Optional)
R2
500 ΚΩ − 1 ΜΩ
XTAL1 XTAL2
Exar UARTTL16C550C
DATA COMMUNICATIONS APPLICATION NOTE
DAN132
2
1.3 FIRMWARE DIFFERENCES
1.3.1 Firmware Differences Between the TL16C550C and ST16C550
The internal registers in the TL16C550C and ST16C550 are similar but with some exceptions:
R = Read-Only, W = Write-Only, R/W = Read/Write
1.3.2 Summary of Differences Between the ST16C550 and TL16C550C
The differences between the ST16C550 and TL16C550C is summarized in the table below.
T
ABLE 1: ST16C550 AND TL16C550C REGISTER SET DIFFERENCES
A2:A0 R/W ST16C550 TL16C550C
LCR Bit-7 = 0
100 R/W Modem Control Register (MCR)
• Bit-5 = Not Used
Modem Control Register (MCR)
• Bit-5 = Auto RTS/CTS Flow Control Enable
TABLE 2: DIFFERENCES BETWEEN EXAR’S ST16C550 WITH TI’S TL16C550C
COMPARISON ST16C550 TL16C550C
Data Bus St and ard Intel Intel
Power Supply Operation 3.3 and 5 V 3.3 and 5 V
Max Operating Current 1.3 mA @ 3. 3 V
3 mA @ 5 V
8 mA @ 3.3 V
10 mA @ 5 V
Max Frequenc y on XTAL1 16 MHz @ 3.3 V
24 MHz @ 5 V
14 MHz @ 3.3 V
16 MHz @ 5 V
Data Sampli ng Rates 16X 16X
BRG Prescaler 1 1
Max Data Rate 1 Mbps @ 3.3 V
1.5 Mbps @ 5 V
875 Kbps @ 3.3 V
1 Mbps @ 5V
Package 44-PLCC, 48-TQFP, 40-PDIP 44-PLCC, 48-TQFP, 40-PDIP
Operating Temperature Ranges Commercial and Industrial Commercial and Industrial
TX/RX FIFO Size 16 16
TX/RX Trigger Tables 1 Trigger Table 1 Trigger Table
TX FIFO Interrupt Trigger Levels 1 1
RX FIFO Interrupt Trigger Levels 4 Selectable 4 Selectable
Hardware Flow Control N/A Auto RTS/CTS Flow Control
Software Flow Control N/A N/A
Infrared Mode N/A N/A
Sleep Mode N/A N/A
Low Power Mode N/A N/A
Diagnostic Modes Local loopback Local Loopback
RS485 Mode N/A N/A