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2015-10-05 - EFM32LG332FXX - d0135_Rev1.10 2

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1 Errata

This document contains information on the errata of the latest revision of this device. For errata on older revisions, please refer to the errata history for the

device. The device data sheet explains how to identify chip revisions, either from package markings or electronically.

In addition to the errata noted below, the errata for the ARM Cortex-M3 r2p1 (www.arm.com) also applies to this device.

1.1 Chip revision E

Table 1.1. Erratas

ID Title/Problem Effect Fix/Workaround

BU_E105 LFXO missing cycles during IOVDD

ramping

LFXO missing cycles during IOVDD

ramping when used in combination

with Backup mode.

When IOVDD is ramped, the dc-level of the XTAL signal

changes, resulting in missed LFXO cycles and possible

glitches on the LFXO clock.

Set PRESC in BURTC_CTRL to greater then 0 when ramp-

ing IOVDD in combination with Backup mode to avoid glitch-

es on the LFXO clock.

CMU_E114 Device not waking up from EM2

when using prescaled non-HFRCO

oscillator as HFCLK

If the device is running from any prescaled oscillator other

than HFRCO as HFCLK and HFRCO is disabled, the device

will not wake up from EM2.

Before entering EM2, clear CMU_CTRL_HFCLKDIV.

Alternatively, enable HFRCO by setting

CMU_OSCENCMD_HFRCOEN and wait until

CMU_STATUS_HFRCORDY is set.

DAC_E109 DAC output drift over lifetime

The voltage output of the DAC might

drift over time.

When the device is powered and the DAC is disabled, stress

on an internal circuit node can cause the output voltage of

the DAC to drift over time, and in some cases may violate the

DACOFFSET

specification. If the DAC is always enabled while

the device is powered, this condition cannot occur.

Both in the startup initialization code and prior to disabling

the DAC in application code, set the OPAnSHORT bit in

DACn_OPACTRL to a '1' for the corresponding DAC(s) used

by the application. This will prevent the output voltage drift

over time effect.

EMU_E107 Interrupts during EM2 entry

An interrupt from a peripheral run-

ning from the high frequency clock

that is received during EM2 entry will

cause the EMU to ignore the SLEEP-

DEEP-flag.

During EM2 entry, the high frequency clocks that are dis-

abled during EM2 will run for some clock cycles after WFI is

issued to allow safe shutdown of the peripherals. If an en-

abled interrupt is requested from one of these non-EM2 pe-

ripherals during this shutdown period, the attempt to enter

EM2 will fail, and the device will enter EM1 instead. As a re-

sult the pending interrupt will immediately wake the device to

EM0.

Before entering EM2, disable all high frequency peripheral in-

terrupts in the core.

PCNT_E102 PCNT Pulse Width Filtering does

not work

The PCNT Pulse Width Filter does not work as intended. Do not use the pulse width filter, i.e. ensure FILT = 0 in

PCNTn_CTRL.