Data Sheet

DS00003669D - 1

Introducon

RTG4 FPGAs integrate Microchip's fourth-generation ash-based FPGA fabric and high-performance interfaces

such as serialization/deserialization (SerDes) on a single-chip while maintaining the resistance to radiation-

induced conguration upsets in the harshest radiation environments, such as space ight (LEO, MEO, GEO,

HEO, deep space), high altitude aviation, medical electronics, and nuclear power plant control. The RTG4

family oers up to 151,824 registers, which are hardened by design against radiation-induced single-event

upsets (SEUs). Each RTG4 logic element includes a 4-input LookUp Table (LUT4) with fast carry chains providing

high-performance FPGA fabric up to 300 MHz.

Multiple embedded memory options and embedded multiply-accumulate blocks perform Digital Signal

Processing (DSP) up to 300 MHz. A high-speed serial interface provides 3.125 Gbps native SerDes

communication, while double data rate DDR2/DDR3/LPDDR memory controllers provide high-speed memory

interfaces.

This datasheet applies to part numbers starting with RT4G150 and 5962-1620.

Device Status

The following table lists the development status of the RTG4 FPGA devices.

Table 1. Device Status

Device Package Status

RT4G150 CGG/LGG/CBG1657 Production

RT4G150 CQG352 Production

RT4G150 FCG/FC1657 Production

RT4G150 CG/LG/CB1657 EOL per PCN JAON-26GOCS315

RT4G150 CQ352 EOL per PCN JAON-26GOCS315

Note: For CQ(G)352 package qualication, Group D5, which includes the salt atmosphere test, is only done with

the device's lid face down.

Technical Briefs and Pin Descripons

The following list shows the technical brief and pin descriptions of the RTG4 FPGAs that are published

separately.

• RTG4 FPGAs Technical Brief

• RTG4 FPGA Pin Descriptions

• RTG4 Plastic Pin Assignment

Export Control Classicaon Number (ECCN)

For ECCN, visit the Microchip webpage for Export Control Data.

RTG4

™

FPGA

Data Sheet

DS00003669D - 2

Table of Contents

Introduction...........................................................................................................................................................................1

Device Status..................................................................................................................................................................1

Technical Briefs and Pin Descriptions.........................................................................................................................1

Export Control Classication Number (ECCN)........................................................................................................... 1

1. General Specications.................................................................................................................................................. 4

1.1. Operating Conditions........................................................................................................................................ 4

2. Power Consumption................................................................................................................................................... 11

2.1. Quiescent Supply Current...............................................................................................................................11

3. Junction Temperature and Derating Factors............................................................................................................12

4. User I/O Characteristics..............................................................................................................................................13

4.1. Input Buer...................................................................................................................................................... 13

4.2. Output Buer and AC Loading.......................................................................................................................14

4.3. Tristate Buer and AC Loading...................................................................................................................... 15

4.4. I/O Speeds.........................................................................................................................................................16

4.5. Detailed I/O Characteristics............................................................................................................................18

4.6. Single-Ended I/O Standards............................................................................................................................19

4.7. Memory Interface and Voltage Reference I/O Standards........................................................................... 31

4.8. Dierential I/O Standards............................................................................................................................... 50

4.9. I/O Register Specications.............................................................................................................................. 65

4.10. DDR Module Specication.............................................................................................................................. 71

5. Logic Element Specications......................................................................................................................................77

5.1. LUT4...................................................................................................................................................................77

5.2. Sequential Module...........................................................................................................................................78

6. Global Resource Characteristics................................................................................................................................81

7. FPGA Fabric SRAM.......................................................................................................................................................86

7.1. FPGA Fabric Large SRAM (LSRAM)..................................................................................................................86

7.2. FPGA Fabric Micro SRAM (µSRAM).................................................................................................................90

8. FPGA Fabric Micro PROM (μPROM)...........................................................................................................................97

9. JTAG............................................................................................................................................................................... 98

9.1. Live Probe......................................................................................................................................................... 98

10. Power-up to Functional Times...................................................................................................................................99

11. Device Reset DEVRST_N............................................................................................................................................100

12. On-Chip Oscillator.....................................................................................................................................................102

13. Clock Conditioning Circuits (CCC)............................................................................................................................ 103

14. System Controller SPI Characteristics.....................................................................................................................106

15. Mathblock Timing Characteristics...........................................................................................................................107