EFR32xG21 Wireless Gecko
Reference Manual
The EFR32xG21 Wireless Gecko SoC is the first device in the Series 2 Wireless Gecko
Portfolio, and includes the EFR32MG21 Mighty Gecko and EFR32BG21 Blue Gecko.
The EFR32xG21 improves processing capability with a Cortex M33 core and has best in
class link budget while providing for lower active current for both the MCU and radio. The
dedicated security core (Secure Engine) provides improved cryptography and hardware
security that is isolated from the main application CPU. This high performance and se-
cure multi-protocol device supports Zigbee, Thread, and Bluetooth 5.0.
The single-die solution provides industry-leading energy efficiency, processing capability,
and RF performance in a small form factor for IoT connected applications.
KEY FEATURES
• 32-bit ARM® Cortex M33 core with 80
MHz maximum operating frequency
• Scalable Memory and Radio configuration
options available in QFN packaging
• Peripheral Reflex System enabling
autonomous interaction of MCU
peripherals
• Autonomous Hardware Crypto Accelerator
and True Random Number Generator
• Multiple Integrated 2.4 GHz PAs with up to
20 dBm transmit power
Security
Secure Debug
Authentication
Timers and Triggers
32-bit bus
Peripheral Reflex System
Serial
Interfaces
I/O Ports Analog I/F
Lowest power mode with peripheral operational:
USART
I
2
C
External
Interrupts
General
Purpose I/O
Pin Reset
Pin Wakeup
IADC
Analog
Comparator
EM4—Shutoff
Energy
Management
Brown-Out
Detector
Voltage
Regulator
Power-On Reset
Clock Management
HF Crystal
Oscillator
LF Crystal
Oscillator
LF
RC Oscillator
HF
RC Oscillator
EM23 HF RC
Oscillator
Crypto Acceleration
Secure Element
Ultra LF RC
Oscillator
Core / Memory
ARM Cortex
TM
M33 processor
with DSP extensions,
FPU and TrustZone
ETM Secure Debug RAM Memory
LDMA
Controller
Flash Program
Memory
Real Time
Capture Counter
Timer/Counter
Low Energy Timer
Watchdog Timer
Protocol Timer
EM3—StopEM2—Deep SleepEM1—SleepEM0—Active
True Random
Number Generator
Fast Startup
RC Oscillator
Back-Up Real
Time Counter
Radio Transceiver
DEMOD
AGC
IFADC
CRC
BUFC
MOD
FRC
RAC
Frequency
Synth
PGA
RF Frontend
I
Q
PA
LNA
PA
EUI
Secure Boot with
Root of Trust and
Secure Loader
DPA
Countermeasures
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Table of Contents
1. About This Document ...........................22
1.1 Introduction ...............................22
1.2 Conventions ...............................23
1.3 Related Documentation ...........................24
2. System Overview .............................25
2.1 Introduction ...............................26
2.2 Block Diagrams..............................27
2.3 MCU Features overview ...........................28
2.4 Security Features .............................29
2.4.1 Secure Boot with Root of Trust and Secure Loader (RTSL) .............29
2.4.2 Cryptographic Accelerator.........................30
2.4.3 True Random Number Generator ......................30
2.4.4 Secure Debug with Lock/Unlock.......................30
2.4.5 DPA Countermeasures..........................30
2.4.6 Secure Key Management with PUF .....................30
2.4.7 Anti-Tamper .............................31
2.4.8 Secure Attestation ...........................31
2.5 Oscillators and Clocks ...........................32
2.6 RF Frequency Synthesizer ..........................32
2.7 Modulation Modes .............................32
2.8 Transmit Mode ..............................33
2.9 Receive Mode ..............................33
2.10 Data Buffering ..............................33
2.11 Unbuffered Data Transfer ..........................33
2.12 Frame Format Support ...........................33
2.13 Hardware CRC Support ..........................34
2.14 Convolutional Encoding / Decoding ......................34
2.15 Binary Block Encoding / Decoding .......................34
2.16 Timers ................................35
2.17 RF Test Modes .............................35
3. System Processor ............................36
3.1 Introduction ...............................36
3.2 Features ................................37
3.3 Functional Description ...........................37
3.3.1 Interrupt Operation ...........................38
3.3.2 TrustZone ..............................38
3.3.3 Interrupt Request Lines (IRQ) .......................39
4. Memory and Bus System ..........................41
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