TECHNICAL
PAPER
Functional Testing of Decoupling
Capacitors for Dynamic Rams
Arch G. Martin
KYOCERA AVX Components Corporation
Myrtle Beach, SC
Ward Parkinson
Micron Technology, Inc.
Boise, Idaho
Abstract
Comparative performance of various types of distributed
decoupling capacitors both with and without bulk tantalum
capacitors is shown under actual operating conditions in a 64K
dynamic RAM memory board designed especially for high-
frequency in-use testing. Multilayer ceramic capacitors are
shown to be effective and economical even without using bulk
tantalum capacitors for decoupling.
Utilization of the new 64K dynamic RAMs in digital
electronic systems requires effective decoupling
capacitors to minimize high-frequency transients in
order to avoid “V bump” or “soft” error problems.
Capacitors must also be capable of supplying bulk
current requirements during the refresh cycle otherwise
undesirable voltage variations (“V droops”) will occur.
Most capacitor specifications still reflect operation at
lower frequencies, higher voltages, and employ dc
testing procedures that are not characteristic of
present high-speed circuits. For today’s applications,
particularly decoupling and bypassing, new methods
of determining the capacitor performance parameters
are required.
AVX has designed and constructed memory test
boards to aid in studying the performance of capacitors
under actual operating conditions. The results of these
tests confirm that a more effective and economical
means of decoupling dynamic RAMs can be obtained by
increasing the capacitance values of the distributed
multilayer ceramic (MLC) capacitors located adjacent to
each memory IC, and by eliminating the high-value
tantalum capacitors at the end of each row of memory
ICs.
Memory Test Boards
Dynamic RAM memory boards were designed and
fabricated to determine board noise level (“V bumps”)
and voltage droop occurring during the refresh cycle.
The two-sided boards (Figure 1) were constructed so as
to permit the testing and comparison of various
decoupling capacitors during actual use in a digital
memory application. Facilities were provided for the
insertion, in various patterns throughout the board, of
capacitors being tested or compared (Figure 2). A
number of test-probe points were placed at various
locations for oscilloscope connections.
The test boards are for use with single power supply
(Vcc = +5V) dynamic RAMs (16 or 64K) in an 8 by 4
array (that is, four rows of memory chips with eight ICs
in each row). Two rows (16 units) were populated for
these tests. A number of DRAMs from various
manufacturers were used to make up several different
boards, although on any given memory board memory
circuits from a single manufacturer were used.
Each test board provides six variables that can be
altered as follows:
Functions: Regular access or refresh only. The regular
access occurs about every 500 ns and this is variable;
the refresh cycles occur about every 2 ms, also variable.
Trigger: Selects signal to scope. The “RAS” pad
provides the scope trigger signal for either regular or
FUNCTIONAL TESTING OF
DECOUPLING CAPACITORS
FOR DYNAMIC RAMs
By Arch G. Martin
KYOCERA AVX Components Corporation
Ward Parkinson
Micron Technology, Inc. Boise, Idaho
Figure 1. Scope Probe Connected to Terminals
on Dynamic RAM Test Board
Figure 2. Inserting Capacitor on Memory Test Board