RX26T Group

Renesas MCUs

Datasheet

R01DS0407EJ0110 Rev.1.10 Page 1 of 138

Aug 10, 2023

Features

■ 32-bit RXv3 CPU core

 Maximum operating frequency: 120 MHz

Capable of 709 CoreMark in operation at 120 MHz

 A collective register bank save function is available.

 Supports the memory protection unit (MPU)

 JTAG and FINE (one-line) debugging interfaces

■ Low-power design and architecture

 Operation from a single 2.7- to 5.5-V supply

 Three low-power modes

■ On-chip code flash memory

 Supports versions with up to 512 Kbytes of ROM

 Operation at 120 MHz (with no waiting)

 User code is programmable by on-board or off-board programming.

 Programming/erasing as background operations (BGOs)

 A dual-bank structure allows exchanging the start-up bank.

■ On-chip data flash memory

 16 Kbytes, reprogrammable up to 100,000 times

 Programming/erasing as background operations (BGOs)

■ On-chip SRAM

 64 K/48Kbytes of SRAM (with no waiting)

■ Data transfer

 DMACAa: 8 channels

 DTCb: 1 channel

■ ELC

 Module operation can be initiated by event signals without using

interrupts

 Linked operation between modules is possible when the CPU is in

sleep mode

■ Reset and supply management

 Power-on reset (POR)

 Low voltage detection (LVD) with voltage settings

■ Clock functions

 The main clock oscillator is connectable to an 8- to 24-MHz external

crystal resonator and usable as the PLL reference clock.

 Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20

MHz

 120-kHz clock for the IWDTa

■ Independent watchdog timer

 120-kHz IWDT-dedicated on-chip oscillator clock operation

■ Useful functions for IEC60730 compliance

 Oscillation-stoppage detection, functions for self-diagnosis and

detection of disconnection for the A/D converter, clock frequency

accuracy measurement circuit, independent watchdog timer, RAM

test-assisting function by DOC, and CRCA, etc.

 Register write protection function can protect values in important

registers against overwriting.

■ Encryption functions (Trusted Secure IP Lite)

 128- or 256-bit key length of AES for ECB, CBC, GCM, others

 True random number generator

 Unauthorized access to the encryption engine is disabled and

imposture and falsification of information are prevented

 Safe management of keys

■ Up to 83 pins for general I/O ports

 5-V tolerance, open drain, input pull-up, switchable driving ability,

and retention of the port output

■ Various communications interfaces

 CAN FD: Compliant with ISO11898-1:2015, standard frame and

extended frame (1 channel)

 SCIk and SCIh with multiple functionalities (up to 4 channels)

Choose from among asynchronous mode, clock-synchronous mode,

smart-card interface mode, simplified SPI, simplified I

C, and

extended serial mode.

 Up to three RSCIs with Manchester encoding and HBS functionality

 I

C bus interface (RIICa) for transfer at up to 400 kbps (fast mode),

capable of SMBus operation (1 channel)

 I3C bus interface (RI3C) for the single data rate (SDR) mode

(1 channel)

 RSPId (1 channel) for transfer at up to 30 Mbps

■ Up to 29 extended-function timers

 32-bit (products with 64 Kbytes of RAM) or 16-bit (products with 48

Kbytes of RAM) GPTWa (8 channels): operation at 120 MHz, input

capture, output compare, PWM waveforms: 10 output channels in

single-phase complementary PWM mode/3 output channels in 3-

phase complementary PWM mode/2 output channels in 5-phase

complementary PWM mode, phase-counting mode, linkage with

comparator (counting operation, PWM negate control)

 16-bit MTU3d (9 channels): operation at 120 MHz, input capture,

output compare, PWM waveforms: 2 output channels in 3-phase

complementary PWM mode, phase-counting mode

 8-bit TMRb (8 channels)

 16-bit CMT (4 channels)

■ High-resolution PWM waveform generation circuit

(HRPWM): 4 channels

 Controlling the timing of rising or falling of the PWM output

waveform for 32-bit GPTWa is realized with minimum of 260 ps

resolution (in operation at 120 MHz)

■ 12-bit A/D converter (S12ADH)

 Products with 64 Kbytes of RAM

Three 12-bit units of sample-and-hold circuit included:

Unit 0 (4 channels for 3 sample-and-hold circuits),

Unit 1 (4 channels for 3 sample-and-hold circuits),

Unit 2 (14 channels)

 Products with 48 Kbytes of RAM

Two 12-bit units of sample-and-hold circuit included:

Unit 0 (7 channels for 3 sample-and-hold circuits),

Unit 2 (8 channels)

■ Analog Comparator (CMPCa): 6 channels

■ 12-bit D/A converter: 2 channels

 Usable as a reference voltage for the analog comparator

■ Temperature sensor for measuring temperature

within the chip

■ Recommended operating temp. range (Topr)

 D-version: –40C to +85C

 G-version: –40C to +105C

PLQP0100KB-B 14 × 14 mm, 0.5 mm pitch

PLQP0080KB-B 12 × 12 mm, 0.5 mm pitch

PLQP0064KB-C 10 × 10 mm, 0.5 mm pitch

PLQP0048KB-B 7 × 7 mm, 0.5 mm pitch

PWQN0064KF-A 9 × 9 mm, 0.5 mm pitch

PWQN0048KC-A 7 × 7 mm, 0.5 mm pitch

120-MHz, 32-bit RX MCU, on-chip FPU, 709 CoreMark, Supportive of 5V power supply,

up to 512-KB flash memory, up to 64-KB SRAM, 16-KB data flash memory, various communications interfaces including

CAN FD, Simultaneous sampling with 3 units of 12-bit A/D converter (up to 7 channels), Analog comparator (6 channels),

120 MHz PWM (4 channels for 3-phase complementary, 2 channels for 5-phase complementary, 10 channels for single-phase

complementary), 4-channel high-resolution PWM with resolution of 260 ps at the minimum, Encryption functions

R01DS0407EJ0110

Rev.1.10

Aug 10, 2023

Features

R01DS0407EJ0110 Rev.1.10 Page 2 of 138

Aug 10, 2023

RX26T Group 1. Overview

1. Overview

1.1 Outline of Specifications

Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different

packages.

Table 1.1 shows the outline of maximum specifications. The peripheral functions and the number of their channels vary

depending on the number of pins of the package, and the RAM capacity. For details, see Table 1.2, Comparison of

Functions for Different Packages.

Table 1.1 Outline of Specifications (1/9)

Classification Module/Function Description

CPU CPU  Maximum operating frequency: 120 MHz

 32-bit RX CPU (RXv3)

 Minimum instruction execution time: One instruction per state (cycle of the system clock)

 Address space: 4-Gbyte linear

 Register set of the CPU

General purpose: Sixteen 32-bit registers

Control: Ten 32-bit registers

Accumulator: Two 72-bit registers

 113 instructions (products with 64 Kbytes of RAM), 111 instructions (products with 48

Kbytes of RAM)

Standard provided instructions: 111

Basic instructions: 77

Single precision floating point instructions: 11

DSP instructions: 23

Instructions for register bank save function: 2 (only supported by products with 64 Kbytes

of RAM)

 Addressing modes: 11

 Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

 On-chip 32-bit multiplier: 32 × 32 → 64 bits

 On-chip divider: 32/32 → 32 bits

 Barrel shifter: 32 bits

FPU  Single-precision (32-bit) floating-point number

 Data types and floating-point exceptions in conformance with the IEEE754 standard

function

 Fast collective saving and restoration of the values of CPU registers

 16 save register banks

Memory Code flash memory  Capacity: 512 Kbytes, 256 Kbytes, 128 Kbytes

 120 MHz No-wait access

 On-board programming: Three types

 Instructions are executable only for the program stored in the TM target area by using the

Trusted Memory (TM) function and protection against data reading is realized.

 A dual-bank structure allows programming during reading or exchanging the start-up

areas

Data flash memory  Capacity: 16 Kbytes

 Programming/erasing: 100,000 times

Unique ID  12-byte unique ID for the device

RAM  Capacity: 64 Kbytes, 48 Kbytes

 120 MHz No-wait access

 SED (single error detection)

Operating modes  Operating modes by the mode-setting pins at the time of release from the reset state

Single-chip mode

Boot mode (SCI interface)

Boot mode (FINE interface)

 Selection of operating mode by register setting

Single-chip mode

 Endian selectable