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SLG7RN46358
RZ/G2E Power Sequence
SLG7RN46358_DS_r100
SLG7RN46358_GP_r001
Rev 1.00
Revised June 06, 2023
General Description
Feat
ures
Output S
ummary
1 Outp
ut
-
O
pen
Drai
n NMOS 2
X
4 Outp
uts
-
Pus
h Pu
ll
1
X
Pin Configuration
Pin na
m
e
Pin #
Pin n
am
e
Pin #
Pin n
am
e
1
GATE_B
17
NC
2
NC
18
NC
3
NC
19
NC
4
NC
20
NC
5
NC
21
NC
6
NC
22
NC
7
SDA
23
NC
8
SCL
24
NC
9
NC
25
NC
10
NC
26
ENABLE
11
NC
27
UVLO_Ato
D
12
GATE_C
28
NC
13
GATE_D
29
NC
14
GND
30
GND
15
VDD2
31
VDD
16
nRESET
32
GATE_A
•
Low Po
wer Con
su
mptio
n
•
Pb
-
Free / RoH
S C
o
mpl
iant
•
Halo
gen
-
Free
•
STQFN
-
32
Pac
ka
ge
Renesas SLG7RN46358 is a l
ow power and small
form
device.
The
SoC
is
housed
in
a
4mm
x
4mm
STQFN
package
which
is
optimal
for
using
with
smal
l d
ev
ic
e
s.
RZ/G2E Power Sequence
SLG7RN46358
Page 2 of
12
SLG7RN46358_DS_r100
Block Diagram