Development Board
EPC9068
Quick Start Guide
EPC8010
100 V Half Bridge with Sync FET Bootstrap Gate Drive
QUICK START GUIDE
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Demonstration System EPC9068
DESCRIPTION
The EPC9068 development board is a 100 V maximum device voltage,
2.7 A maximum output current, half bridge with onboard gate drives,
featuring the EPC8010 enhancement mode (eGaN®) eld eect transistor
(FET). The gate driver has been congured with a synchronous FET
bootstrap circuit featuring the EPC2038 eGaN FET that eliminates high
side device losses induced by the reverse recovery losses of the internal
bootstrap diode of the gate driver. The purpose of this development
board is to simplify the evaluation process of the EPC8010 eGaN FET by
including all the critical components on a single board that can be easily
connected into any existing converter. The inclusion of the synchronous
FET bootstrap circuit enables signicant increase in operating frequency
capability of the half bridge circuit.
The EPC9068 development board is 2” x 1.5” and has two EPC8010 eGaN
FETs in a half bridge conguration using Texas Instruments LM5113 gate
driver with supply and bypass capacitors. The board contains all critical
components and layout for optimal switching performance. There are
also various probe points to facilitate simple waveform measurement
and eciency calculation. The board includes pads for the inclusion of
customer components to facilitate testing in a Buck converter or ZVS
class-D amplier congurations. A complete block diagram of the circuit
is given in gure 1.
For more information on the EPC8010 and EPC2038 eGaN FETs please
refer to the datasheet available from EPC at www.epc-co.com. The
datasheet should be read in conjunction with this quick start guide.
Table 1: Performance Summary (T
A
= 25°C) EPC9068
Symbol Parameter Conditions Min Max Units
V
DD
Gate Drive Input Supply
Range
7.5 12 V
V
IN
Bus Input Voltage Range 80* V
V
OUT
Switch Node Output Voltage 100 V
I
OUT
Switch Node Output Current 2.7* A
V
PWM
PWM Logic Input Voltage
Threshold
Input ‘High’
Input ‘Low’
3.5
0
6
1.5
V
V
Minimum ‘High’ State Input
Pulse Width
V
PWM
rise and
fall time < 10ns
40 ns
Minimum ‘Low’ State Input
Pulse Width
V
PWM
rise and
fall time < 10ns
160# ns
*Assumes inductive load, maximum current depends on die temperature – actual maximum current
with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
QUICK START PROCEDURE
Development board EPC9068 is easy to set up to evaluate the
performance of the EPC8010 eGaN FET. Refer to gure 2 for proper
connect and measurement setup and follow the procedure below:
1. Congure the board for either ZVS class-D operation OR Buck converter
operation.
2. With power o, connect the input power supply bus to +V
IN
(J1) and
ground / return to –V
IN
(J4).
3. For ZVS class-D operation, with power o, connect a HF load to the HF
output (RF-J2 OR V
SW
-J3 and GND-J4). For Buck converter operation,
with power o, connect a DC load to the DC output (+V
OUT
-J5 and
GND-J4).
4. With power o, connect the gate drive input to +V
DD
(J90, Pin-1) and
ground return to –V
DD
(J90, Pin-2).
5. With power o, connect the input PWM control signal to PWM
(J70, Pin-1) and ground return to either Pin-2 or Pin-4 of J70.
6. Turn on the gate drive supply – make sure the supply is within the
7.5 V and 12 V range.
7. Turn on the controller / PWM input source and probe switching node
to observe switching operation.
8. Turn on the bus voltage to the required value (do not exceed the
absolute maximum voltage of 52 V on V
OUT
). Increase voltage slowly
while monitoring operation to ensure the FETs are operating within
their datasheet parameters.
9. Once operational, adjust the bus voltage and load PWM control
within the operating range and observe the output switching
behavior, eciency and other parameters.
10. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node, care
must be taken to avoid long ground leads. Measure the switch node by
placing the oscilloscope probe tip through the large via on the switch
node (designed for this purpose) and grounding the probe directly
across the GND terminal provided. See gure 3 for proper scope probe
technique.
EPC9068 development board